Abstract: A programming system for programming an electrically programmable gate array (EPGA) provides a clocked data signal with data cycles of the form 01DD, where the 01 ensures a clock transition each data cycle and the DD constitutes two bit periods with the same data value. The timing is led by a timing sequence of the form 0100. The EPGA measures the period of the timing sequence. For each data cycle, the EPGA detects the 01 transition, then, after a delay equal to twice the measured timing sequence period, generates a clock pulse. The series of clock pulses so generated constitutes a configuration clock. The configuration clock is used to time sampling of the clocked data signal to extract a configuration data signal. The configuration clock and the configuration data signal are used in a conventional manner to program configuration EPROMs of the EPGA.