Abstract: A medication dosage timing apparatus which measures and displays time in response to the opening and closing of a medication bottle or container. A timing circuit and display are mounted on a circuit board and attached to a container cap. A battery is mounted on a disk which slidably moves within the container cap between a first position wherein electrical contacts on the circuit board engage the battery and activate or power the timing circuit and display, and a second position wherein the electrical contacts are disengaged from the battery and the timing circuit and display are deactivated. When the container cap is attached to the container, the battery and disk are held in the first activating position, and when the container cap is removed from the container, the battery and disk slide down into second, deactivating position. Each time a user opens and closes the medication container, the timing circuit and display are reset and re-started.

Abstract: A system and method for operating a Broadband ISDN to support a viable virtual private network (VPN) service are attained by establishing a plurality of virtual path links connecting customer locations and broadband switching systems, by cross-connecting virtual channel links at the broadband switching systems to establish end-to-end virtual channel connections, and by policing both the input and output traffic only on the virtual path links. An egress policing processor is included at each output port on broadband switches to police the traffic on each virtual path link which contains one customer's multiplexed virtual channel connection traffic.

Abstract: A digital phase locked loop operable over a wide dynamic range has jitter performance that is exactly bounded within predetermined limits. The phase locked loop includes an accumulator-type digital voltage controlled oscillator (201) which generates from a high speed system clock, an output clock signal at frequency equal to p times the frequency of an input clock signal, and which output frequency is controlled by the value k of a digital input to the VCO. A frequency window comparator (208) compares the number of output clock pulses between input clock pulses to determine, based on the count, whether the frequency of the output is too high, too low or equal to the correct frequency. A phase window comparator (210) simultaneously determines from the phase of the output clock signal whether the phase is leading, lagging or within a prescribed window of acceptability.

Abstract: In order to multiplex a plurality of various rate subchannels onto a fixed rate channel, a frame structure is defined consisting of j tuples of bits. Some of the tuples are i bits long and some are less than i, the sum of the bits less than i in these tuples being equal to k where k is greater than or equal to zero. The total number of bits per frame is thus equal to ij-k where i, j and k are mathematically determined as a function of the rates of the subchannels and the rate of the fixed channel. In one tuple of i bits in each frame, all bits are set ZERO. In each other tuple, the last bit is set ONE. Framing is detected by monitoring for a ONE followed by i ZEROes a pattern which cannot occur elsewhere in the frame regardless of the data. This frame arrangement can yield shorter frames than the frame structure disclosed in U.S. Pat. No. 4,617,658, thus decreasing reframe time.

Abstract: A plurality of various rate digital subchannels are multiplexed onto a fixed rate channel by arranging the data bits from the subchannels into a framing structure consisting of j sets of i-tuples for ij bits per frame where the parameters i and j are mathematically determined as a junction of the rates of the subchannels and the rate of the fixed channel. Framing is maintained by setting each bit in the first i-tuple to ZERO and the last bit in each other i-tuple to ONE. A multiplexer-demultiplexer is described which is adaptive to the rates of the subchannels and the fixed channel in this frame structure and which can therefore be employed for any mix of subchannel and fixed channel rates.

Abstract: In order to multiplex a plurality of various rate subchannels onto a fixed rate channel, a frame structure is defined consisting of j sets of i-tuples for a total of ij bits per frame, the parameters i and j being mathematically determined as a function of the rate of the subchannels and the rate of the fixed channel. For j-l of the i-tuples, i-l bits are used for information and the last bit is set ONE. In one i-tuple all i bits are set ZERO. Framing is detected by monitoring for a ONE followed by i ZEROes, a pattern which cannot occur elsewhere in the frame regardless of the data. An integral number of information bits from each subchannel are distributed in the (i-l)(j-l) information bit positions. In the disclosed embodiment two 6662/3 bps channels and a 4800 bps channel are multiplexed onto an 8000 bps channel using a frame structure consisting of 24 quintets. In the 92 information bit positions, 72 bits are allocated for the 4800 bps channel and 10 bits each are allocated for the 6662/3 bps channels.

Abstract: A bit compression multiplexer (FIG. 2) for a pair of time division multiplexed digital bit streams each one of which includes a plurality of PCM encoded signals deposited in separate and distinct channels of a repetitive frame and signaling bits multiplexed therewith. The PCM encoded signals of successive frames are normally bit compressed (23) into n-bit signals, but periodically the encoded signals of a frame are bit compressed into n-1 bit signals. The bit compressed signals of the pair of bit streams are time division multiplexed (24) with each other, with the multiplexed compressed signals occupying separate and distinct channels of a repetitive frame. The signaling bits are extracted (21) from the pair of digital bit streams and are inserted (24) into predetermined n-1 bit channels of the last-recited repetitive frame. The signaling bits that are placed in a given channel are related to the encoded message signal of that channel.

Abstract: A bit compression coding circuit incorporates signaling bit insertion. An input signal sample(s) representing, for example, PCM encoded speech or voiceband data, is delivered to a difference circuit (31) where a predicted signal (s.sub.e) is subtracted from it. The predicted signal is an estimate of the input sample derived from a predictor (32). The resultant difference signal is coupled to the input of an adaptive quantizer (34) which provides at its output a bit compressed quantized differential PCM version of the difference signal. A multiplexer (37) receives the output of the quantizer and serves to periodically preempt the least significant bit of the bit compressed PCM signal and substitute a signaling bit therefor. The output of the multiplexer is coupled to the input of an adder (38) wherein it is added to the predicted signal.

Abstract: A data control circuit (18) for an input/output arrangement is arranged for controlling the transfer of a data word through a shift register (20 or 120) to or from a peripheral device (22 or 122). The circuit (18) provides for selection between internal clock generation at one of several rates or application of an external clock and for selection of the length and format of the data words to be transferred. Selection is accomplished by an interval counter (38), format data stored in a control register (37), two gating circuits (30 and 40) and a selection circuit (35).