Patents by Inventor Stephen Mancini

Stephen Mancini has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Stress relief in semiconductor wafers
    Patent number: 11990425
    Abstract: This disclosure describes a method for fabricating a plurality of semiconductor devices in a semiconductor wafer includes: bowing a semiconductor wafer including a substrate by covering the substrate with a strained layer; forming trenches at locations in scribe lines of the semiconductor wafer, the scribe lines identifying areas between adjacent dies on the semiconductor wafer; and reducing the bowing of the semiconductor wafer by filling the trenches with a stress-compensation material.
    Type: Grant
    Filed: August 18, 2021
    Date of Patent: May 21, 2024
    Assignee: Tokyo Electron Limited
    Inventors: Hojin Kim, Stephen Mancini, Soo Doo Chae
  • Stress Relief in Semiconductor Wafers
    Publication number: 20220102289
    Abstract: This disclosure describes a method for fabricating a plurality of semiconductor devices in a semiconductor wafer includes: bowing a semiconductor wafer including a substrate by covering the substrate with a strained layer; forming trenches at locations in scribe lines of the semiconductor wafer, the scribe lines identifying areas between adjacent dies on the semiconductor wafer; and reducing the bowing of the semiconductor wafer by filling the trenches with a stress-compensation material.
    Type: Application
    Filed: August 18, 2021
    Publication date: March 31, 2022
    Inventors: Hojin Kim, Stephen Mancini, Soo Doo Chae