Patents by Inventor Stephen McConnell Gates

Stephen McConnell Gates has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20030001240
    Abstract: Novel semiconductor devices containing a discontinuous cap layer and possessing a relatively low dielectric constant are provide herein. The novel semiconductor devices includes at least a substrate, a first dielectric layer applied on at least a portion of the substrate, a first set of openings formed through the dielectric layer to expose the surface of the substrate so that a conductive material deposited within and filling the openings provides a first set of electrical contact conductive elements and a discontinuous layer of cap material covering at least the top of the conductive elements to provide a first set of discontinuous cap elements. Methods for forming the semiconductor devices are also provided.
    Type: Application
    Filed: July 2, 2001
    Publication date: January 2, 2003
    Applicant: International Business Machiness Corporation
    Inventors: Stanley Joseph Whitehair, Stephen McConnell Gates, Sampath Purushothaman, Satyanarayana V. Nitta, Maurice McGlashan-Powell, Kevin S. Petrarca
  • Publication number: 20020196594
    Abstract: An over voltage spike or surge protection principle is provided that involves an element that is positioned between a node in the circuitry and a reference voltage that performs as an insulator as voltage across the element increases and at a selectable voltage, the current at any higher voltage such as during a spike or a surge is shunted to reference or ground, the element is not damaged by the breakdown type of the effect of the shunting of the current, and then, after the duration of the high voltage excursion the element returns to the performance before the selectable voltage. The principle of the invention permits in-situ or locallized over voltage protection to selected nodes throughout circuitry as well as throughout an integrated circuit including the interface with external circuitry.
    Type: Application
    Filed: June 21, 2001
    Publication date: December 26, 2002
    Inventors: Stephan Alan Cohen, John Anthony Fitzsimmons, Stephen McConnell Gates, Alfred Grill
  • Publication number: 20020172811
    Abstract: A diffusion barrier that has a low dielectric constant, k, yet resistant to oxygen and/or moisture permeability is provided. The diffusion barrier includes a dielectric stack having at least two or more dielectric films, each film having a dielectric constant of about 8 or less, wherein the dielectric stack comprises alternating films composed of a high-permeability material and a low-permeability material. A semiconductor structure including substrate having at least one wiring region and the inventive diffusion barrier formed on a surface of the substrate is also provided.
    Type: Application
    Filed: May 16, 2001
    Publication date: November 21, 2002
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Edward Paul Barth, Stephan A. Cohen, Chester Dziobkowski, John Anthony Fitzsimmons, Stephen McConnell Gates, Thomas Henry Ivers, Sampath Purushothaman, Darryl D. Restaino, Horatio Seymour Wildman
  • Patent number: 6479110
    Abstract: A low dielectric constant, multiphase material which can be used as an interconnect dielectric in IC chips is disclosed. Also disclosed is a method for fabricating a multiphase low dielectric constant film utilizing a plasma enhanced chemical vapor deposition technique. Electronic devices containing insulating layers of the multiphase low dielectric constant materials that are prepared by the method are further disclosed.
    Type: Grant
    Filed: September 27, 2001
    Date of Patent: November 12, 2002
    Assignee: International Business Machines Corporation
    Inventors: Alfred Grill, Vishnubhai Vitthalbhai Patel, Stephen McConnell Gates
  • Publication number: 20020164891
    Abstract: A porous, low-k dielectric film that has good mechanical properties as well as a method of fabricating the film and the use of the film as a dielectric layer between metal wiring features are provided. The porous, low-k dielectric film includes a first phase of monodispersed pores having a diameter of from about 1 to about 10 nm that are substantially uniformly spaced apart and are essentially located on sites of a three-dimensional periodic lattice; and a second phase which is solid surrounding the first phase. Specifically, the second phase of the film includes (i) an ordered element that is composed of nanoparticles having a diameter of from about 1 to about 10 nm that are substantially uniformly spaced apart and are essentially arranged on sites of a three-dimensional periodic lattice, and (ii) a disordered element comprised of a dielectric material having a dielectric constant of about 2.8 or less.
    Type: Application
    Filed: May 3, 2001
    Publication date: November 7, 2002
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Stephen McConnell Gates, Christopher B. Murray, Satyanarayana V. Nitta, Sampath Purushothaman
  • Publication number: 20020145200
    Abstract: A spin-on cap useful as a post-CMP cap for Cu interconnect structures is provided. The inventive spin-on cap includes a low-k dielectric (on the order of 3.5 or less) and at least one additive. The at least one additive employed in the present invention is capable of binding Cu ions, and is soluble in the spun-on low-k dielectric. The spin-on cap of the present invention may further include a spun-on low-k (on the order of 3.5 or less) reactive-ion etch (RIE) stop layer. Spin-on caps containing a bilayer of low-dielectric plus at least additive and low-k RIE stop layer are preferred. It is noted that the inventive spin-on cap of the present invention does not significantly increase the effective dielectric constant of the interconnect structure and does not add additional cost to the fabrication of the interconnect structure since a single deposition tool, i.e., spin coating tool, is employed. Moreover, because of the presence of the additive in the spin-on cap, Cu migration is substantially minimized.
    Type: Application
    Filed: April 5, 2001
    Publication date: October 10, 2002
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Timothy Joseph Dalton, Stephen McConnell Gates, Jeffrey Curtis Hedrick, Satyanarayana V. Nitta, Sampath Purushothaman, Christy Sensenich Tyberg
  • Publication number: 20020117760
    Abstract: A low-k dielectric metal conductor interconnect structure having no micro-trenches present therein and a method of forming such a structure are provided. Specifically, the above structure is achieved by providing an interconnect structure which includes at least a multilayer of dielectric materials which are applied sequentially in a single spin apply tool and then cured in a single step and a plurality of patterned metal conductors within the multilayer of spun-on dielectrics. The control over the conductor resistance is obtained using a buried etch stop layer having a second atomic composition located between the line and via dielectric layers of porous low-k dielectrics having a first atomic composition. The inventive interconnect structure also includes a hard mask which assists in forming the interconnect structure of the dual damascene-type.
    Type: Application
    Filed: February 28, 2001
    Publication date: August 29, 2002
    Applicant: INTERNATIONAL BUSINESS CORPORATION
    Inventors: Stephen McConnell Gates, Jeffrey Curtis Hedrick, Satyanarayana V. Nitta, Sampath Purushothaman, Christy Sensenich Tyberg
  • Publication number: 20020119654
    Abstract: A cost effective and simple method of patterning interconnect structures is provided in which spun-on materials are used as the hard mask. The use of spun-on materials for the hard mask ensures that the process is carried out in a single tool and it permits the use of a single curing step which is not typically employed in prior art patterning processes wherein CVD hard masks are employed. The effective dielectric constant of the resultant structure is not significantly increased since the use of spin coating allows for selection of a polish stop layer (formed on a surface of a low-k dielectric) that has substantially the same dielectric constant as the underlying dielectric. In the present invention, the hard mask employed includes at least two spun-on dielectric materials that have different etch rates.
    Type: Application
    Filed: February 28, 2001
    Publication date: August 29, 2002
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ann Rhea-Helene Fornof, Stephen McConnell Gates, Jeffrey Curtis Hedrick, Satyanarayana V. Nitta, Sampath Purushothaman, Christy Sensenich Tyberg
  • Publication number: 20020117737
    Abstract: An interconnect structure including a patterned multilayer of spun-on dielectrics as well as methods for manufacturing the same are provided. The interconnect structure includes a patterned multilayer of spun-on dielectrics formed on a surface of a substrate. The patterned multilayer of spun-on dielectrics is composed of a bottom low-k dielectric, a buried etch stop layer, and a top low-k dielectric, wherein the bottom and top low-k dielectrics have a first composition, the said buried etch stop layer has a second composition which is different from the first composition and the buried etch stop layer is covalently bonded to said top and bottom low-k dielectrics. The interconnect structure further includes a polish stop layer formed on the patterned multilayer of spun-on dielectrics; and metal conductive regions formed within the patterned multilayer of spun-on dielectrics.
    Type: Application
    Filed: February 28, 2001
    Publication date: August 29, 2002
    Applicant: INTERNATIONAL BUSINESS CORPORATION
    Inventors: Stephen McConnell Gates, Jeffrey Curtis Hedrick, Satyanarayana V. Nitta, Sampath Purushothaman, Cristy Sensenich Tyberg
  • Publication number: 20020117754
    Abstract: A metal wiring plus low-k dielectric interconnect structure of the dual damascene-type is provided wherein the conductive metal lines and vias are built into a hybrid low-k dielectric which includes two spun-on dielectrics that have different atomic compositions and at least one of the two spun-on dielectrics is porous. The two spun-on dielectrics used in forming the inventive hybrid low-k dielectric each have a dielectric constant of about 2.6 or less, preferably each dielectric of the hybrid structure has a k of from about 1.2 to about 2.2. By utilizing the inventive hybrid low-k dielectric excellent control over metal line resistance (trench depth) is obtained, without no added cost. This is achieved without the use of a buried etch stop layer, which if present, would be formed between the two spun-on dielectrics.
    Type: Application
    Filed: February 28, 2001
    Publication date: August 29, 2002
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Stephen McConnell Gates, Jeffrey Curtis Hedrick, Satyanarayana V. Nitta, Sampath Purushothaman, Christy Sensenich Tyberg
  • Patent number: 6440560
    Abstract: The present invention relates to a novel organosilicon particle having the formula SiaObCcHd. The particle may be coated with an organic film, preferably a rigid connector compound. The present invention also provides a method of using the organosilicon particle and/or rigid connector compound in the formation of a low-k dielectric film.
    Type: Grant
    Filed: July 26, 1999
    Date of Patent: August 27, 2002
    Assignee: International Business Machines Corporation
    Inventors: Stephen McConnell Gates, Christopher Bruce Murray
  • Patent number: 6437443
    Abstract: A low dielectric constant, multiphase material which can be used as an interconnect dielectric in IC chips is disclosed. Also disclosed is a method for fabricating a multiphase low dielectric constant film utilizing a plasma enhanced chemical vapor deposition technique. Electronic devices containing insulating layers of the multiphase low dielectric constant materials that are prepared by the method are further disclosed.
    Type: Grant
    Filed: September 27, 2001
    Date of Patent: August 20, 2002
    Assignee: International Business Machines Corporation
    Inventors: Alfred Grill, Vishnubhai Vitthalbhai Patel, Stephen McConnell Gates
  • Publication number: 20020094438
    Abstract: The present invention relates to a novel organosilicon particle having the formula SiaObCcHd. The particle may be coated with an organic film, preferably a rigid connector compound. The present invention also provides a method of using the organosilicon particle and/or rigid connector compound in the formation of a low-k dielectric film.
    Type: Application
    Filed: January 24, 2002
    Publication date: July 18, 2002
    Applicant: International Business Machines Corporation
    Inventors: Stephen McConnell Gates, Christopher Bruce Murray
  • Publication number: 20020093075
    Abstract: An apparatus and method is described incorporating one or more layers of SiCOH and one or more layers of patterned conductors in an integrated circuit chip. The invention overcomes the problem of capacitance by lowering the k of the delectric and overcomes the problem of breakdown voltage and the leakage curent by tailoring the composition of SiCOH.
    Type: Application
    Filed: January 14, 2002
    Publication date: July 18, 2002
    Applicant: International Business Machines Corporation
    Inventors: Stephen McConnell Gates, Alfred Grill
  • Publication number: 20020037442
    Abstract: A low dielectric constant, multiphase material which can be used as an interconnect dielectric in IC chips is disclosed. Also disclosed is a method for fabricating a multiphase low dielectric constant film utilizing a plasma enhanced chemical vapor deposition technique. Electronic devices containing insulating layers of the multiphase low dielectric constant materials that are prepared by the method are further disclosed.
    Type: Application
    Filed: September 27, 2001
    Publication date: March 28, 2002
    Applicant: International Business Machines Corporation
    Inventors: Alfred Grill, Vishnubhai Vitthalbhai Patel, Stephen McConnell Gates
  • Publication number: 20020034625
    Abstract: A low dielectric constant, multiphase material which can be used as an interconnect dielectric in IC chips is disclosed. Also disclosed is a method for fabricating a multiphase low dielectric constant film utilizing a plasma enhanced chemical vapor deposition technique. Electronic devices containing insulating layers of the multiphase low dielectric constant materials that are prepared by the method are further disclosed.
    Type: Application
    Filed: September 27, 2001
    Publication date: March 21, 2002
    Applicant: International Business Machines Corporation
    Inventors: Alfred Grill, Vishnubhai Vitthalbhai Patel, Stephen McConnell Gates
  • Patent number: 6351023
    Abstract: A semiconductor device such as a P-N or P-I-N junction diode, includes a first semiconductor layer having a first conductivity-type and being mounted over a metal address line, and a second semiconductor layer having a second conductivity-type and being mounted over the first semiconductor material. The diode preferably has a thickness of substantially no more than about 1 micron, and the diode includes a P-N junction confined to a thickness of less than about 0.1 micron. In the preferred embodiment the method comprises depositing a first semiconductor layer having a first conductivity type, depositing a second intrinsic layer, annealing to convert both layers to a polycrystalline layer, implanting ions of a second conductivity type into the second layer, and annealing to convert the second layer to a polycrystalline. The result is a diode having an ultra-sharp p-n junction.
    Type: Grant
    Filed: October 13, 2000
    Date of Patent: February 26, 2002
    Assignee: International Business Machines Corporation
    Inventors: Stephen McConnell Gates, Roy Edwin Scheuerlein
  • Patent number: 6312793
    Abstract: A low dielectric constant, multiphase material which can be used as an interconnect dielectric in IC chips is disclosed. Also disclosed is a method for fabricating a multiphase low dielectric constant film utilizing a plasma enhanced chemical vapor deposition technique. Electronic devices containing insulating layers of the multiphase low dielectric constant materials that are prepared by the method are further disclosed.
    Type: Grant
    Filed: May 26, 1999
    Date of Patent: November 6, 2001
    Assignee: International Business Machines Corporation
    Inventors: Alfred Grill, Vishnubhai Vitthalbhai Patel, Stephen McConnell Gates
  • Publication number: 20010028059
    Abstract: The present invention describes the use of two semiconductor layers, a thin film (TF) layer and a bulk Si wafer layer, to make high density and high speed merged logic and memory IC chips. The memory cells use three-dimensional (3D) SRAM structures. Two kinds of 3D logic cells are disclosed. 3D form of the differential cascode voltage switch (DCVS) architecture, and a 3D form of the DCVS with pass gate (DCVSPG) logic architecture. A high density “system on chip” architecture is described. The high density is achieved by locating large PMOS transistors in the TF Si layer, and the fast NMOS transistors in a bulk Si wafer layer. A single process sequence to simultaneously make the logic and memory circuits on the IC chip is also described.
    Type: Application
    Filed: May 18, 2001
    Publication date: October 11, 2001
    Inventors: Philip George Emma, Wei Hwang, Stephen McConnell Gates
  • Patent number: 6285050
    Abstract: The present invention describes the use of large thin film (TF) capacitors having capacitance C made in a separate set of TF layers ABOVE the Si and wiring levels of an integrated circuit (IC). This C is very large. This invention describes a two-level IC architecture in which a metal/insulator/metal (MIM) capacitor structure comprises the upper level, and CMOS logic and memory circuits made in the Si wafer substrate comprise the lower level. The added thin film capacitance serves to stabilize the power supply voltage at a constant level during GHz IC operation.
    Type: Grant
    Filed: December 24, 1997
    Date of Patent: September 4, 2001
    Assignee: International Business Machines Corporation
    Inventors: Philip George Emma, Wei Hwang, Stephen McConnell Gates