Abstract: An IC alignment mark in a contact metal layer for use under an opaque layer, and a process for forming the alignment mark, are disclosed. The alignment mark includes contact metal fields, each several microns wide, with an array of PMD pillars in the interior, formed during contact etch, contact metal deposition and selective contact metal removal processes. The pillars are arrayed such that all exposed surfaces of the contact metal are planar. One configuration is a rectangular array in which every other row is laterally offset by one-half of the column spacing. Horizontal dimensions of the pillars are selected to maximize the contact metal fill factor, while providing sufficient adhesion to the underlying substrate during processing. The contact metal is at least 15 nanometers lower than the PMD layer surrounding the alignment mark, as a result of the contact metal removal process.

Abstract: An IC alignment mark in a contact metal layer for use under an opaque layer, and a process for forming the alignment mark, are disclosed. The alignment mark includes contact metal fields, each several microns wide, with an array of PMD pillars in the interior, formed during contact etch, contact metal deposition and selective contact metal removal processes. The pillars are arrayed such that all exposed surfaces of the contact metal are planar. One configuration is a rectangular array in which every other row is laterally offset by one-half of the column spacing. Horizontal dimensions of the pillars are selected to maximize the contact metal fill factor, while providing sufficient adhesion to the underlying substrate during processing. The contact metal is at least 15 nanometers lower than the PMD layer surrounding the alignment mark, as a result of the contact metal removal process.

Abstract: An IC alignment mark in a contact metal layer for use under an opaque layer, and a process for forming the alignment mark, are disclosed. The alignment mark includes contact metal fields, each several microns wide, with an array of PMD pillars in the interior, formed during contact etch, contact metal deposition and selective contact metal removal processes. The pillars are arrayed such that all exposed surfaces of the contact metal are planar. One configuration is a rectangular array in which every other row is laterally offset by one-half of the column spacing. Horizontal dimensions of the pillars are selected to maximize the contact metal fill factor, while providing sufficient adhesion to the underlying substrate during processing. The contact metal is at least 15 nanometers lower than the PMD layer surrounding the alignment mark, as a result of the contact metal removal process.

Abstract: An IC alignment mark in a contact metal layer for use under an opaque layer, and a process for forming the alignment mark, are disclosed. The alignment mark includes contact metal fields, each several microns wide, with an array of PMD pillars in the interior, formed during contact etch, contact metal deposition and selective contact metal removal processes. The pillars are arrayed such that all exposed surfaces of the contact metal are planar. One configuration is a rectangular array in which every other row is laterally offset by one-half of the column spacing. Horizontal dimensions of the pillars are selected to maximize the contact metal fill factor, while providing sufficient adhesion to the underlying substrate during processing. The contact metal is at least 15 nanometers lower than the PMD layer surrounding the alignment mark, as a result of the contact metal removal process.

Abstract: The present invention provides a method for manufacturing a digital micromirror device and a method for manufacturing a projection display system. The method for manufacturing the digital micromirror device, without limitation, may include providing a material stack, the material stack including a spacer layer having one or more openings therein and located over control circuitry located on or in a semiconductor substrate, a layer of hinge material located over the spacer layer and within the one or more openings, and a layer of hinge support material located over the layer of hinge material and within the one or more openings. The method may further include patterning the layer of hinge support material using photoresist, patterning the layer of hinge material using the patterned layer of hinge support material as a hardmask, and removing the patterned layer of hinge support material from over an upper surface of the patterned layer of hinge material.

Abstract: The present invention provides a method for manufacturing a digital micromirror device and a method for manufacturing a projection display system. The method for manufacturing the digital micromirror device may include providing a material stack, the material stack including a spacer layer having one or more openings therein and located over control circuitry located on or in a semiconductor substrate, a layer of hinge material located over the spacer layer and within the one or more openings, and a layer of hinge support material located over the layer of hinge material and within the one or more openings. The method may further include patterning the layer of hinge support material using photoresist, patterning the layer of hinge material using the patterned layer of hinge support material as a hardmask, and removing the patterned layer of hinge support material from over an upper surface of the patterned layer of hinge material.

Abstract: The present invention provides a method for manufacturing a digital micromirror device and a method for manufacturing a projection display system. The method for manufacturing the digital micromirror device, without limitation, may include providing a material stack (130), the material stack (130) including a spacer layer (140) having one or more openings (145) therein and located over control circuitry (110) located on or in a semiconductor substrate (105), a layer of hinge material (150) located over the spacer layer (140) and within the one or more openings (145), and a layer of hinge support material (160) located over the layer of hinge material (150) and within the one or more openings (145).

Abstract: A method for controlling linewidth in photolithography and in particular during the fabrication of integrated circuits involves separately introducing a linewidth control feature onto a substrate or wafer. This linewidth control feature is preferably introduced after the desired design features or codes and is introduced using the same photomask or reticle as the desired design features. This photomask preferably includes the linewidth control feature at a point outside the maximum field zone as well as a masked pad portion that is in the maximum field zone. This masked pad portion is introduced with the desired design features and serves as a location for subsequent exposure of the linewidth control features. The method allows for the variation in linewidth introduced by the lens to be minimized, or even eliminated, since the same portion of the lens field can be used to expose each linewidth control feature.