Patents by Inventor Stephen Mobley
Stephen Mobley has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10262915Abstract: The present disclosure relates to a thermally enhanced semiconductor package, which includes a module substrate, a thinned flip chip die over the substrate, a first mold compound component, and a thermally enhanced mold compound component. The first mold compound component resides over the module substrate, surrounds the thinned flip chip die, and extends above an upper surface of the thinned flip chip die to form a cavity over the upper surface of the thinned flip chip die. The thermally enhanced mold compound component includes a lower portion filling a lower region of the cavity and residing over the upper surface of the thinned flip chip die, and an upper portion filling an upper region of the cavity and residing over the lower portion. A first average thermal conductivity of the lower portion is at least 1.2 times greater than a second average thermal conductivity of the upper portion.Type: GrantFiled: March 7, 2018Date of Patent: April 16, 2019Assignee: Qorvo US, Inc.Inventors: Julio C. Costa, George Maxim, Dirk Robert Walter Leipold, Baker Scott, Merrill Albert Hatcher, Jr., Stephen Mobley
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Patent number: 10229860Abstract: The present disclosure relates to a thermally enhanced semiconductor package, which includes a module substrate, a thinned flip chip die over the substrate, a first mold compound component, and a thermally enhanced mold compound component. The first mold compound component resides over the module substrate, surrounds the thinned flip chip die, and extends above an upper surface of the thinned flip chip die to form a cavity over the upper surface of the thinned flip chip die. The thermally enhanced mold compound component includes a lower portion filling a lower region of the cavity and residing over the upper surface of the thinned flip chip die, and an upper portion filling an upper region of the cavity and residing over the lower portion. A first average thermal conductivity of the lower portion is at least 1.2 times greater than a second average thermal conductivity of the upper portion.Type: GrantFiled: March 7, 2018Date of Patent: March 12, 2019Assignee: Qorvo US, Inc.Inventors: Julio C. Costa, George Maxim, Dirk Robert Walter Leipold, Baker Scott, Merrill Albert Hatcher, Jr., Stephen Mobley
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Patent number: 10192803Abstract: The present disclosure relates to a thermally enhanced semiconductor package, which includes a module substrate, a thinned flip chip die over the substrate, a first mold compound component, and a thermally enhanced mold compound component. The first mold compound component resides over the module substrate, surrounds the thinned flip chip die, and extends above an upper surface of the thinned flip chip die to form a cavity over the upper surface of the thinned flip chip die. The thermally enhanced mold compound component includes a lower portion filling a lower region of the cavity and residing over the upper surface of the thinned flip chip die, and an upper portion filling an upper region of the cavity and residing over the lower portion. A first average thermal conductivity of the lower portion is at least 1.2 times greater than a second average thermal conductivity of the upper portion.Type: GrantFiled: March 7, 2018Date of Patent: January 29, 2019Assignee: Qorvo US, Inc.Inventors: Julio C. Costa, George Maxim, Dirk Robert Walter Leipold, Baker Scott, Merrill Albert Hatcher, Jr., Stephen Mobley
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Patent number: 10153223Abstract: The present disclosure relates to a thermally enhanced semiconductor package, which includes a module substrate, a thinned flip chip die over the substrate, a first mold compound component, and a thermally enhanced mold compound component. The first mold compound component resides over the module substrate, surrounds the thinned flip chip die, and extends above an upper surface of the thinned flip chip die to form a cavity over the upper surface of the thinned flip chip die. The thermally enhanced mold compound component includes a lower portion filling a lower region of the cavity and residing over the upper surface of the thinned flip chip die, and an upper portion filling an upper region of the cavity and residing over the lower portion. A first average thermal conductivity of the lower portion is at least 1.2 times greater than a second average thermal conductivity of the upper portion.Type: GrantFiled: March 7, 2018Date of Patent: December 11, 2018Assignee: Qorvo US, Inc.Inventors: Julio C. Costa, George Maxim, Dirk Robert Walter Leipold, Baker Scott, Merrill Albert Hatcher, Jr., Stephen Mobley
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Publication number: 20180322247Abstract: Methods, systems, and computer readable storage media relate to processing and analyzing a sample to determine presence or concentration of at least one sensor target in a sample. A method of quantifying a sample using a sensor may include obtaining sensor data, the sensor data including in-situ calibration data from a housekeeping protein; analyzing the sensor data; and outputting results of the analyzing. The method may be used with a system that includes a sensing device and a module. The system may also include an analysis device that can be in communication with the sensing device.Type: ApplicationFiled: February 21, 2018Publication date: November 8, 2018Inventors: Paul W. Doetsch, Dong Moon Shin, Carlos Sanchez Moreno, William D. Hunt, Georgia Zhuo Chen, Sunil Yalamanchili, Stephen Mobley
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Patent number: 10103080Abstract: The present disclosure relates to a thermally enhanced semiconductor package, which includes a module substrate, a thinned flip chip die over the substrate, a first mold compound component, and a thermally enhanced mold compound component. The first mold compound component resides over the module substrate, surrounds the thinned flip chip die, and extends above an upper surface of the thinned flip chip die to form a cavity over the upper surface of the thinned flip chip die. The thermally enhanced mold compound component includes a lower portion filling a lower region of the cavity and residing over the upper surface of the thinned flip chip die, and an upper portion filling an upper region of the cavity and residing over the lower portion. A first average thermal conductivity of the lower portion is at least 1.2 times greater than a second average thermal conductivity of the upper portion.Type: GrantFiled: November 16, 2016Date of Patent: October 16, 2018Assignee: Qorvo US, Inc.Inventors: Julio C. Costa, George Maxim, Dirk Robert Walter Leipold, Baker Scott, Merrill Albert Hatcher, Jr., Stephen Mobley
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Patent number: 10026669Abstract: The present disclosure relates to a thermally enhanced semiconductor package, which includes a module substrate, a thinned flip chip die over the substrate, a first mold compound component, and a thermally enhanced mold compound component. The first mold compound component resides over the module substrate, surrounds the thinned flip chip die, and extends above an upper surface of the thinned flip chip die to form a cavity over the upper surface of the thinned flip chip die. The thermally enhanced mold compound component includes a lower portion filling a lower region of the cavity and residing over the upper surface of the thinned flip chip die, and an upper portion filling an upper region of the cavity and residing over the lower portion. A first average thermal conductivity of the lower portion is at least 1.2 times greater than a second average thermal conductivity of the upper portion.Type: GrantFiled: November 16, 2016Date of Patent: July 17, 2018Assignee: Qorvo US, Inc.Inventors: Julio C. Costa, George Maxim, Dirk Robert Walter Leipold, Baker Scott, Merrill Albert Hatcher, Jr., Stephen Mobley
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Publication number: 20180197803Abstract: The present disclosure relates to a thermally enhanced semiconductor package, which includes a module substrate, a thinned flip chip die over the substrate, a first mold compound component, and a thermally enhanced mold compound component. The first mold compound component resides over the module substrate, surrounds the thinned flip chip die, and extends above an upper surface of the thinned flip chip die to form a cavity over the upper surface of the thinned flip chip die. The thermally enhanced mold compound component includes a lower portion filling a lower region of the cavity and residing over the upper surface of the thinned flip chip die, and an upper portion filling an upper region of the cavity and residing over the lower portion. A first average thermal conductivity of the lower portion is at least 1.2 times greater than a second average thermal conductivity of the upper portion.Type: ApplicationFiled: March 7, 2018Publication date: July 12, 2018Inventors: Julio C. Costa, George Maxim, Dirk Robert Walter Leipold, Baker Scott, Merrill Albert Hatcher, Jr., Stephen Mobley
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Patent number: 9997426Abstract: The present disclosure relates to a thermally enhanced semiconductor package, which includes a module substrate, a thinned flip chip die over the substrate, a first mold compound component, and a thermally enhanced mold compound component. The first mold compound component resides over the module substrate, surrounds the thinned flip chip die, and extends above an upper surface of the thinned flip chip die to form a cavity over the upper surface of the thinned flip chip die. The thermally enhanced mold compound component includes a lower portion filling a lower region of the cavity and residing over the upper surface of the thinned flip chip die, and an upper portion filling an upper region of the cavity and residing over the lower portion. A first average thermal conductivity of the lower portion is at least 1.2 times greater than a second average thermal conductivity of the upper portion.Type: GrantFiled: November 16, 2016Date of Patent: June 12, 2018Assignee: Qorvo US, Inc.Inventors: Julio C. Costa, George Maxim, Dirk Robert Walter Leipold, Baker Scott, Merrill Albert Hatcher, Jr., Stephen Mobley
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Patent number: 9960095Abstract: The present disclosure relates to a thermally enhanced semiconductor package, which includes a module substrate, a thinned flip chip die over the substrate, a first mold compound component, and a thermally enhanced mold compound component. The first mold compound component resides over the module substrate, surrounds the thinned flip chip die, and extends above an upper surface of the thinned flip chip die to form a cavity over the upper surface of the thinned flip chip die. The thermally enhanced mold compound component includes a lower portion filling a lower region of the cavity and residing over the upper surface of the thinned flip chip die, and an upper portion filling an upper region of the cavity and residing over the lower portion. A first average thermal conductivity of the lower portion is at least 1.2 times greater than a second average thermal conductivity of the upper portion.Type: GrantFiled: November 16, 2016Date of Patent: May 1, 2018Assignee: Qorvo US, Inc.Inventors: Julio C. Costa, George Maxim, Dirk Robert Walter Leipold, Baker Scott, Merrill Albert Hatcher, Jr., Stephen Mobley
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Patent number: 9922898Abstract: The present disclosure relates to a thermally enhanced semiconductor package, which includes a module substrate, a thinned flip chip die over the substrate, a first mold compound component, and a thermally enhanced mold compound component. The first mold compound component resides over the module substrate, surrounds the thinned flip chip die, and extends above an upper surface of the thinned flip chip die to form a cavity over the upper surface of the thinned flip chip die. The thermally enhanced mold compound component includes a lower portion filling a lower region of the cavity and residing over the upper surface of the thinned flip chip die, and an upper portion filling an upper region of the cavity and residing over the lower portion. A first average thermal conductivity of the lower portion is at least 1.2 times greater than a second average thermal conductivity of the upper portion.Type: GrantFiled: November 16, 2016Date of Patent: March 20, 2018Assignee: Qorvo US, Inc.Inventors: Julio C. Costa, George Maxim, Dirk Robert Walter Leipold, Baker Scott, Merrill Albert Hatcher, Jr., Stephen Mobley
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Patent number: 9892987Abstract: The present disclosure relates to a thermally enhanced semiconductor package, which includes a module substrate, a thinned flip chip die over the substrate, a first mold compound component, and a thermally enhanced mold compound component. The first mold compound component resides over the module substrate, surrounds the thinned flip chip die, and extends above an upper surface of the thinned flip chip die to form a cavity over the upper surface of the thinned flip chip die. The thermally enhanced mold compound component includes a lower portion filling a lower region of the cavity and residing over the upper surface of the thinned flip chip die, and an upper portion filling an upper region of the cavity and residing over the lower portion. A first average thermal conductivity of the lower portion is at least 1.2 times greater than a second average thermal conductivity of the upper portion.Type: GrantFiled: November 16, 2016Date of Patent: February 13, 2018Assignee: Qorvo US, Inc.Inventors: Julio C. Costa, George Maxim, Dirk Robert Walter Leipold, Baker Scott, Merrill Albert Hatcher, Jr., Stephen Mobley
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Publication number: 20170358511Abstract: The present disclosure relates to a thermally enhanced semiconductor package, which includes a module substrate, a thinned flip chip die over the substrate, a first mold compound component, and a thermally enhanced mold compound component. The first mold compound component resides over the module substrate, surrounds the thinned flip chip die, and extends above an upper surface of the thinned flip chip die to form a cavity over the upper surface of the thinned flip chip die. The thermally enhanced mold compound component includes a lower portion filling a lower region of the cavity and residing over the upper surface of the thinned flip chip die, and an upper portion filling an upper region of the cavity and residing over the lower portion. A first average thermal conductivity of the lower portion is at least 1.2 times greater than a second average thermal conductivity of the upper portion.Type: ApplicationFiled: November 16, 2016Publication date: December 14, 2017Inventors: Julio C. Costa, George Maxim, Dirk Robert Walter Leipold, Baker Scott, Merrill Albert Hatcher, JR., Stephen Mobley
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Patent number: 6327342Abstract: The present invention is an E911 backup system that bridges and monitors standard analog E911 trunks in an emergency 911 answering system (“E911”), also know as a public safety answering position (PSAP) equipment. The E911 backup system has the ability to take control of these trunks in the event of primary PSAP equipment failure. This is accomplished by monitoring and selectively acting upon a series of alarm signals. The alarm signals include: a watchdog signal from the E911 call answering system; a batter monitor to detect the presence of a voltage on the E911 analog trunk; a wink watch signal to monitor whether the primary systems transmits a wink signal; and an answer alarm signal that detects the E911 call answering systems failure to answer an incoming call within a specified period of time.Type: GrantFiled: May 26, 2000Date of Patent: December 4, 2001Inventors: Matthew Stephen Mobley, Simon J. G. Machell