Abstract: Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, an electronic package comprises a package substrate, and a die on the package substrate. In an embodiment, the electronic package further comprises a voltage regulator on the package substrate adjacent to the die, and a metal printed circuit board (PCB) heat spreader. In an embodiment, a trace on the metal PCB heat spreader couples the die to the voltage regulator.

Abstract: A device may include a plurality of chiplets stacked on top of each other. Each chiplet includes: one or more electronic components; a plurality of connections electrically connecting the one or more electronic components, the plurality of connections formed in one or more metal layers; main surfaces and side surfaces, wherein the main surfaces of adjacent chiplets of the plurality of chiplets face each other. The device may further include an electrically conductive connection formed on at least one side surface of at least one chiplet of the plurality of chiplets to electrically connect one or more connections of the plurality of connections of one or more chiplets of the plurality of chiplets.

Abstract: An apparatus includes a memory, comprising a plurality of stacked memory layers, each stacked memory layer comprising a plurality of memory cells; a memory controller, coupled to the memory along a first signal path, and configured to read a bit from, or store a bit on, a memory cell of the plurality of memory cells; and a logic unit, coupled to the memory via a second signal path, different from the first signal path; wherein the logic unit is configured to read a stored value from the memory, or to save a value to the memory, using the second signal path.

Abstract: In embodiments, a memory device includes a memory including at least one memory die layer and a memory controller operatively coupled to the memory. The memory controller is configured to: obtain read/write request for a targeted portion of the memory; obtain data from the targeted portion of the memory in response to the read/write request; and perform a hybrid data correction on the portion of the targeted memory. Performing the hybrid data correction includes performing a Reed Solomon error correction on the data from targeted memory portion; performing Erasure error correction on the data from the targeted memory portion; and correct the targeted memory portion based on outputs of the performed Reed Solomon error correction and the performed Erasure error correction.

Abstract: A device may include a first die, including: a data transmission interface configured to inductively transmit and receive signals; a processor configured to generate a transmission asynchronous pattern; receive a response pattern via the data transmission interface indicating whether the transmission asynchronous pattern was received by a second die; control a data transfer between the first die and the second die via the data transmission interface based on the response pattern; and a second die, including: a data transmission interface configured to inductively transmit and receive signals; a processor configured to receive the transmission asynchronous pattern; check whether the received transmission asynchronous pattern is correct; generate a response pattern indicating whether the received transmission asynchronous pattern is correct; control a data transfer between the first die and the second die via the data transmission interface based on the check whether the received transmission asynchronous patte

Abstract: Technologies for conformal power delivery structures near high-speed signal traces are disclosed. In one embodiment, a dielectric layer may be used to keep a power delivery structure spaced apart from high-speed signal traces, preventing deterioration of signals on the high-speed signal traces due to capacitive coupling to the power delivery structure.

Abstract: Various aspects relate to electronic memory devices and mechanisms for communicating with electronic memory devices. A plurality of stacked semiconductor wafers forms a wafer stack. A logic base die is configured to support the plurality of stacked semiconductor wafers. At least one through silicon via is formed through the plurality of stacked semiconductor wafers, wherein the at least one through silicon via is configured to form an inductive coil that is configured to provide a communication interface to the plurality of stacked semiconductor wafers.

Abstract: Disclosed herein are microelectronic assemblies, as well as related apparatuses and methods. In some embodiments, a microelectronic assembly may include a plurality of dies stacked vertically; a trench of dielectric material extending through the plurality of dies; a conductive via extending through the trench of dielectric material; and a plurality of conductive pathways between the plurality of dies and the conductive via, wherein individual ones of the conductive pathways are electrically coupled to the conductive via and to individual ones of the plurality of dies, and wherein the individual ones of the plurality of conductive pathways have a first portion including a first material and a second portion including a second material different from the first material.

Abstract: A rotary oscillator array (ROA) apparatus includes a plurality of rotary traveling wave oscillators (RTWOs) configured to generate a plurality of resonant clock signals. An RTWO of the plurality of RTWOs includes a plurality of inverter cells and a fractional divider. The inverter cells are coupled in parallel to each other between two metal interconnects. The fractional divider is coupled to the two metal interconnects. The fractional divider will output a resonant clock signal of the plurality of resonant clock signals based on a reset-out signal generated by a reset-out terminal of the RTWO.

Abstract: A processing circuit includes a plurality of circuit blocks connected in series to a high-voltage supply and a voltage equalizer. The plurality of circuit blocks includes a corresponding plurality of voltage supply terminals and a corresponding plurality of ground terminals. Each circuit block of the plurality of circuit blocks includes a voltage supply terminal of the plurality of voltage supply terminals and a ground terminal of the plurality of ground terminals. At least two of the plurality of circuit blocks are serially coupled to each other. The voltage equalizer includes a plurality of equalizer terminals. An equalizer terminal of the plurality of equalizer terminals is coupled to a corresponding voltage supply terminal of the plurality of voltage supply terminals. The voltage supply terminal of at least one circuit block of the plurality of circuit blocks is coupled to a high-voltage source.

Abstract: Disclosed herein are devices, systems, and methods for driving inductive links in a memory such as a z-axis memory. The memory includes a first memory cell connected via a first inductive link comprising a first pair of double coils and a second memory cell connected via a second inductive link comprising a second pair of double coils. The first inductive link is arranged adjacent to the second inductive link. A driver circuit is configured to simultaneously drive the first and second pair of double coils with a drive current to read or write the first and second memory cells using the first and second inductive links.

Abstract: Technologies for high throughput additive manufacturing (HTAM) structures are disclosed. In one embodiment, a sacrificial dielectric is formed to provide a negative mask on which to pattern a conductive trace using HTAM. In another embodiment, a permanent dielectric is patterned using a processing such as laser project patterning. A conductive trace can then be patterned using HTAM. In yet another embodiment, conductive traces with tapered sidewalls can be patterned, and then a buffer layer and HTAM layer can be deposited on top.

Abstract: Technologies for high throughput additive manufacturing (HTAM) structures are disclosed. In one embodiment, a sacrificial dielectric is formed to provide a negative mask on which to pattern a conductive trace using HTAM. In another embodiment, a permanent dielectric is patterned using a processing such as laser project patterning. A conductive trace can then be patterned using HTAM. In yet another embodiment, conductive traces with tapered sidewalls can be patterned, and then a buffer layer and HTAM layer can be deposited on top.

Abstract: Microelectronic devices, assemblies, and systems include a multichip architecture having one or more integrated circuit dies over and bonded to a base die, and a metallization network over the integrated circuit die(s). A backside metallization of the integrated circuit die(s) is proximal to the metallization network and a frontside metallization of the integrated circuit die(s) is opposite a device layer from the backside metallization. A via lateral to the base die couples to the metallization network to provide an electrical routing to the backside metallization of the integrated circuit die(s) through the via and the metallization network.

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate, having a surface, including a first conductive pathway electrically coupled to a power source; an insulating material on the surface of the package substrate; a first microelectronic component, having a first surface facing the package substrate and an opposing second surface, embedded in the insulating material; a second microelectronic component, having a first surface facing the package substrate and an opposing second surface, embedded in the insulating material; a redistribution layer on the insulating material including a second conductive pathway electrically coupled to the second surface of the second microelectronic component and the second surface of the first microelectronic component; and a wire bond electrically coupling the first and the second conductive pathways.

Abstract: Technologies for micro-LED optical communication via glass waveguides are disclosed. In an illustrative embodiment, a glass interposer is mounted on a circuit board, and several integrated circuit (IC) dies are positioned above the glass interposer. A micro-LED assembly is mounted on each of the IC dies. Waveguides defined in the glass interposer can carry light between the micro-LED assemblies of the various IC dies, providing a high-bandwidth connection between the IC dies. The micro-LED assemblies can provide low-power, high-bandwidth connectivity between the IC dies and can operate in the high-temperature environment near the IC dies.

Abstract: Technologies for back side micro-LED assemblies are disclosed. In an illustrative embodiment, a micro-LED assembly includes several micro-LEDs and several photodiodes mounted on a base die. The base die is mounted on an integrated circuit (IC) die, such as a processor die. Through-silicon vias are defined in the IC die to carry electrical signals between the micro-LED assembly and transistors and other components near or at the front side of the IC die. An optical plug with an optical cable is positioned above the micro-LED assembly to couple light to and from the micro-LEDs and photodiodes. The short distance between the transistors on the front side of the IC die and the micro-LED assembly allows for high-bandwidth signals to be converted to optical signals with little loss. The optical cable can connect IC dies on the same circuit board, in the same housing, in the same rack, etc.

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate including a first conductive pathway; a mold material on the package substrate including a first microelectronic component embedded in the mold material, a second microelectronic component embedded in the mold material, and a TMV, between the first and second microelectronic components, the TMV electrically coupled to the first conductive pathway; a redistribution layer (RDL) on the mold material including a second conductive pathway electrically coupled to the TMV; and a third microelectronic component on the RDL and electrically coupled to the second conductive pathway, wherein the second conductive pathway electrically couples the TMV, the first microelectronic component, and the third microelectronic component.

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate, having a surface, including a first conductive pathway electrically coupled to a power source; a first microelectronic component, having an active side electrically coupled to the surface of the package substrate and an opposing back side, surrounded by an insulating material; a second microelectronic component, having an active side electrically coupled to the surface of the package substrate and an opposing back side, surrounded by the insulating material and including a through-substrate via (TSV) electrically coupled to the first conductive pathway; and a redistribution layer (RDL), on the insulating material, including a second conductive pathway electrically coupling the TSV, the second surface of the second microelectronic component, and the second surface of the first microelectronic component.

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate including a first conductive pathway electrically coupled to a power source; a mold material on the package substrate including a first microelectronic component embedded in the mold material, a second microelectronic component embedded in the mold material, and a TMV, between the first and second microelectronic components, the TMV electrically coupled to the first conductive pathway; a redistribution layer (RDL) on the mold material including a second conductive pathway electrically coupled to the TMV; and a third microelectronic component on the RDL and electrically coupled to the second conductive pathway, wherein the second conductive pathway electrically couples the TMV, the first microelectronic component, and the third microelectronic component.