Patents by Inventor Stephen N. JENKINS

Stephen N. JENKINS has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11757726
    Abstract: A hardware system for simulating a network physical layer for communication channels. The hardware system includes a plurality of hardware processors configurable to model a physical layer and communication channels. The hardware system includes a first interface coupled to the plurality of hardware processors. The first interface is configured to be coupled to a software simulator comprising a physics model configured to provide model parameters based on modeled communication hardware and a temporal modeling scenario. A second interface is coupled to the plurality of hardware processors. The second interface is configured to be coupled to simulated or real nodes for sending and receiving network data to and from the nodes. The hardware processors are configured to model effects of the physical layer and communication channels on the network data.
    Type: Grant
    Filed: May 12, 2021
    Date of Patent: September 12, 2023
    Assignee: L3HARRIS TECHNOLOGIES, INC.
    Inventors: Seth J. Thorup, Kyle R. Morrey, Stephen N. Jenkins, Brent A. Kenney, Benjamin C. Dean, Lee F. Carter
  • Patent number: 11683239
    Abstract: A system for simulating lost data packets. The system includes a first hardware register storing data for fast factors. The fast factors include factors that are time independent with respect to particular data packets. A second hardware register stores slow factors. The slow factors include factors that are time dependent on data packets. Synchronization hardware is coupled to the second hardware register and synchronizes the slow factors with specific data inputs based on dependencies on the data packets. A hardware adder is coupled to the first hardware register and the second hardware register to compute a link budget. The link budget is used in determine probability of loss of data packets. A hardware processor coupled to the hardware adder determines, based on the link budget, if a data packet should be dropped, and when the data packet should be dropped, drops the data packet for simulating a network physical layer.
    Type: Grant
    Filed: May 12, 2021
    Date of Patent: June 20, 2023
    Assignee: L3HARRIS TECHNOLOGIES, INC.
    Inventors: Seth J. Thorup, Kyle R. Morrey, Stephen N. Jenkins, Brent A. Kenney
  • Patent number: 11570056
    Abstract: A hardware system for simulating a network physical layer for communication channels. The hardware system includes a plurality of hardware processors configurable to model a network physical layer and communication channels. The hardware system further includes a multi-point data switch configured to be coupled to various data log points associated with the plurality of hardware processors. The hardware system further includes a RAM coupled to the multi-point data switch, where the RAM is configured to store log data provided by the multi-point data switch as software defined data structures.
    Type: Grant
    Filed: May 12, 2021
    Date of Patent: January 31, 2023
    Assignee: L3HARRIS TECHNOLOGIES, INC.
    Inventors: Stephen N. Jenkins, Kyle R. Morrey, Seth J. Thorup, Alex J. Marcum, David A. Reed
  • Publication number: 20220368599
    Abstract: A system for simulating lost data packets. The system includes a first hardware register storing data for fast factors. The fast factors include factors that are time independent with respect to particular data packets. A second hardware register stores slow factors. The slow factors include factors that are time dependent on data packets. Synchronization hardware is coupled to the second hardware register and synchronizes the slow factors with specific data inputs based on dependencies on the data packets. A hardware adder is coupled to the first hardware register and the second hardware register to compute a link budget. The link budget is used in determine probability of loss of data packets. A hardware processor coupled to the hardware adder determines, based on the link budget, if a data packet should be dropped, and when the data packet should be dropped, drops the data packet for simulating a network physical layer.
    Type: Application
    Filed: May 12, 2021
    Publication date: November 17, 2022
    Inventors: Seth J. THORUP, Kyle R. MORREY, Stephen N. JENKINS, Brent A. KENNEY
  • Publication number: 20220368601
    Abstract: A hardware system for simulating a network physical layer for communication channels. The hardware system includes a plurality of hardware processors configurable to model a network physical layer and communication channels. The hardware system is further implemented where the hardware processors are configured such that a single set of hardware, including a single set of gates and registers, is used in a single simulation to model a plurality of virtual routers for different nodes.
    Type: Application
    Filed: May 12, 2021
    Publication date: November 17, 2022
    Inventors: Kyle R. MORREY, Christopher S. HEFFERNAN, Seth J. THORUP, Stephen N. JENKINS, Stephen M. DUDLEY
  • Publication number: 20220368598
    Abstract: A hardware system for simulating a network physical layer for communication channels. The hardware system includes a plurality of hardware processors configurable to model a physical layer and communication channels. The hardware system includes a first interface coupled to the plurality of hardware processors. The first interface is configured to be coupled to a software simulator comprising a physics model configured to provide model parameters based on modeled communication hardware and a temporal modeling scenario. A second interface is coupled to the plurality of hardware processors. The second interface is configured to be coupled to simulated or real nodes for sending and receiving network data to and from the nodes. The hardware processors are configured to model effects of the physical layer and communication channels on the network data.
    Type: Application
    Filed: May 12, 2021
    Publication date: November 17, 2022
    Inventors: Seth J. THORUP, Kyle R. MORREY, Stephen N. JENKINS, Brent A. KENNEY, Benjamin C. DEAN, Lee F. CARTER
  • Publication number: 20220368600
    Abstract: A hardware system for simulating a network physical layer for communication channels. The hardware system includes a plurality of hardware processors configurable to model a network physical layer and communication channels. The hardware system further includes a multi-point data switch configured to be coupled to various data log points associated with the plurality of hardware processors.
    Type: Application
    Filed: May 12, 2021
    Publication date: November 17, 2022
    Inventors: Stephen N. JENKINS, Kyle R. MORREY, Seth J. THORUP, Alex J. MARCUM, David A. REED
  • Publication number: 20220366097
    Abstract: One embodiment illustrated herein includes a hardware system for simulating a network physical layer for communication channels. The hardware system includes a plurality of hardware processors configurable to model a network physical layer and communication channels. The hardware processors include an opcode processing unit. The hardware processors further include a programmable state machine coupled to the opcode processing unit. The programmable state machine is configured to be programmed by the opcode processing unit using a low-level hardware programming language comprising opcodes having waveform processing specific semantics so as to configure the state machine for specific waveforms or specific network physical layer characteristics.
    Type: Application
    Filed: May 12, 2021
    Publication date: November 17, 2022
    Inventors: Kyle R. MORREY, Stephen N. JENKINS, Seth J. THORUP