Patents by Inventor Stephen N. Kiel

Stephen N. Kiel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7281223
    Abstract: The teachings of the present invention provide a method for modeling an integrated circuit system including a microchip, an integrated circuit package, and a printed circuit board. The method includes generating a configuration file including parasitics regarding ball grid arrays and vias intended for use in design of the integrated circuit system. A netlist may be generated using the configuration file. In accordance with a particular embodiment of the present invention, the operation of the integrated circuit system may be simulated to determine anticipated operating characteristics of the integrated circuit system.
    Type: Grant
    Filed: December 16, 2004
    Date of Patent: October 9, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Stephen N. Kiel, Snehamay Sinha, Gregory E. Howard
  • Patent number: 6986113
    Abstract: A method for estimating noise in an integrated circuit substrate. A model file is created for a technology process for fabricating the integrated circuit. Noise generated by a digital circuit and input/output circuitry to be implemented in the integrated circuit are estimated. A substrate netlist is generated for the integrated circuit. A floorplan is determined for the integrated circuit. Transient simulations are run with predetermined input values. Finally, it is determined if predetermined noise requirements are met in results of the transient simulations.
    Type: Grant
    Filed: November 10, 2003
    Date of Patent: January 10, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Snehamay Sinha, Bipasha Ghosh, Raghu Nandan Srinivasa, Stephen N. Kiel
  • Publication number: 20040187085
    Abstract: A method for estimating noise in an integrated circuit substrate. A model file is created for a technology process for fabricating the integrated circuit. Noise generated by a digital circuit and input/output circuitry to be implemented in the integrated circuit are estimated. A substrate netlist is generated for the integrated circuit. A floorplan is determined for the integrated circuit. Transient simulations are run with predetermined input values. Finally, it is determined if predetermined noise requirements are met in results of the transient simulations.
    Type: Application
    Filed: November 10, 2003
    Publication date: September 23, 2004
    Inventors: Snehamay Sinha, Bipasha Ghosh, Raghu Nandan Srinivasa, Stephen N. Kiel