Abstract: A phase comparator circuit for use with a digital phase-locked loop which can be programmably altered to provide phase comparisons either on the leading edge or leading and trailing edges of the phase-locked loop output signal, to provide an increased operating bandwidth capability to the phase comparator circuit. The phase comparator circuit can be configured to cooperate with a multiple frequency digital phase-locked loop such that the results of a phase comparison will be delayed until a frequency adjustment has been completed.

Abstract: A decoding system and method is disclosed for a radiotelephone system carrying digital messages. A set of multibit high auto-correlation, low cross-correlation synchronization words and their ones complement inverses are employed for message synchronization and supervisory functions. System state communication is achieved by utilizing a sequence of normal synchronization words and their ones complement inverses. Reliability of the coding is achieved by detecting normal or inverse words as binary levels when fewer than a predetermined number of bit errors exist in the bit sequence. If the predetermined number of bit errors is exceeded, a selected binary one or zero is substituted. This selected sequence of binary levels is decoded and the Hamming distance between a masked decoded sequence and a masked selected sequence is calculated.

Abstract: A digital lock detector for a phase-locked loop accumulates out-of-lock pulses which are derived from a high frequency clock signal. The out-of-lock pulses are gated by an out-of-phase indicator signal and a pulse centered around the phase-locked loop output cycles to reduce the effect of relative phase jitter between the input and output signals of the phase-locked loop. The digital lock detector utilizes two counters in series which are reset independently to provide resistance to fading signal conditions. In addition, the lock detector circuit requires several consecutive long out-of-lock indications before an out-of-lock condition is indicated.

Abstract: An improved multiple frequency digital phase-locked loop circuit is described. The improved digital phase-locked loops utilizes a single circuit to effect both phase and frequency adjustments. The multiple frequency digital phase-locked loop effects phase adjustments by selectively combining or subtracting a reference clock signal with a derived programmable clock signal thereby generating a composite digital phase-locked loop clock signal. The multiple frequency provides frequency adjustments by selectively adding or subtracting pulses from the composite clock signal at a rate determined by a programmably controllable clock signal. The improved multifrequency digital phase-locked loop is suitable for use as a tone detector with the addition of a lock detector wherein the phase-locked loop can be programmed for a plurality of known operating frequencies.

Abstract: A unitary phase and frequency adjust network for use in a multiple frequency digital phase-locked loop circuit is described. The unitary phase and frequency adjust network utilizes a single circuit to effect both phase and frequency adjustments. The multiple frequency digital phase-locked loop effects phase adjustments by selectively combining or subtracting a reference clock signal with a derived programmable clock signal thereby generating a composite digital phase-locked loop clock signal. The phase and frequency adjust network effects frequency shifts by selectively adding or subtracting pulses from the composite clock signal at a rate determined by a programmably controlled clock signal.

Abstract: A method for synchronizing the scrambling sequences of communicating scrambler units of a privacy communications system in a reliable and secure manner. The method is particularly adapted for use in noisy or fade prone transmission environments, and permits late entry of authorized third parties to the system. The method utilizes digital sequences interleaved periodically with scrambled analog information to provide reliable synchronization.

Abstract: A digital demodulator for differential phase shift keyed (DPSK) signals includes two pairs of 1-bit integrators for continuously taking the phase difference between successive DPSK bits. Each DPSK bit is subdivided into a plurality of bits, for example 15 bits. A weighted output signal having 4 bits is provided by each 1-bit integrator for each of the bits corresponding to a DPSK bit. The weighted output signals from each pair of 1-bit integrators are sine weighted and multiplied. The products are then added together for application to a comparator. The comparator compares the sum of the addition to a predetermined reference signal and provides a demodulated digital signal having a logical state dependent on whether the sum is greater or smaller than the predetermined reference signal.