Abstract: A radio frequency (RF) transmitter is coupled to and controlled by a processor to transmit data. A physical layer circuit is coupled to the RF transmitter to encode and decode between a digital signal and a modulated analog signal. The physical layer circuit comprises a high rate physical layer circuit (HRP) and a low rate physical layer circuit (LRP). The low rate channels generated by the low rate physical layer circuit (LRP) share a same frequency band as a corresponding high rate channel generated by the high rate physical layer circuit (HRP).

Abstract: A radio frequency (RF) transmitter is coupled to and controlled by a processor to transmit data. A physical layer circuit is coupled to the RF transmitter to encode and decode between a digital signal and a modulated analog signal. The physical layer circuit comprises a high rate physical layer circuit (HRP) and a low rate physical layer circuit (LRP). The low rate channels generated by the low rate physical layer circuit (LRP) share a same frequency band as a corresponding high rate channel generated by the high rate physical layer circuit (HRP).

Abstract: An improved method and apparatus for Viterbi Algorithm calculations for maximum likelihood sequence estimators in communication receivers is disclosed. The calculations for the maximum likelihood sequence estimator, in accordance with the invention, utilizes a variant of the Viterbi algorithm developed by Ungerboeck in which the associated branch metric calculations for the trellis require the computation of a set of branch metric parameters. An embodiment of the present invention provides for an improved recursive method and apparatus for calculation of the branch metric parameters that reduces the number of processor clock cycles required per state metric calculation. This enables real time computation of the branch metric parameters during execution of the Viterbi Algorithm.

Abstract: A system and method for reading and writing in a multilevel optical data system is disclosed. The system provides control signals for timing acquisition, level calibration, DC control, AGC, equalizer training and data synchronization. The user data is ECC protected and optionally convolutionally encoded before being combined with the control signals in an information block. The multilevel information block can be written to an optical disc as a series of multilevel marks. The optical disc may also contain an Address in Pregroove signal (AIP) to facilitate synchronization during writing of an information block. The AIP signal has an integer number of address frames per information block.

Abstract: A system and method for reading and writing in a multilevel optical data system is disclosed. The system provides control signals for timing acquisition, level calibration, DC control, AGC, equalizer training and data synchronization. The user data is ECC protected and optionally convolutionally encoded before being combined with the control signals in an information block. The multilevel information block can be written to an optical disc as a series of multilevel marks. The optical disc may also contain an Address in Pregroove signal (AIP) to facilitate synchronization during writing of an information block. The AIP signal has an integer number of address frames per information block.

Abstract: A system and method for reading and writing in a multilevel optical data system is disclosed. The system provides control signals for timing acquisition, level calibration, DC control, AGC, equalizer training and data synchronization. The user data is ECC protected and optionally convolutionally encoded before being combined with the control signals in an information block. The multilevel information block can be written to an optical disc as a series of multilevel marks. The optical disc may also contain an Address in Pregroove signal (AIP) to facilitate synchronization during writing of an information block. The AIP signal has an integer number of address frames per information block.

Abstract: An electronic device may receive a packet comprising a plurality of codewords comprising pre-processing logic, a first decoder, and a second decoder. The pre-processing logic causes some of said codewords to be provided to the first decoder and other of said codewords to be provided to the second decoder. The codewords may be of different lengths and/or different code rates. Further, the first and second decoders may implement the same or different decoding technique.