Abstract: Provided is a circuit for signalling the real-time end of a local area network packet as the packet is being pulled off a transmission medium and stored in memory. Storage of the packet is performed by a local area network coprocessor. The circuit monitors for the simultaneous occurrence of three conditions: the coprocessor is in a write-to-memory cycle; it is writing to the address of a status word pertaining to a packet; and the most significant bit of the status word is being set. If all three conditions are true, the circuit asserts the real-time end-of-packet signal.

Abstract: Provided is a circuit for preventing local area network packets shorter than a predetermined bit length from being received by a local area network coprocessor. Serial data which would otherwise be received by the coprocessor is delayed by a data-shift register of predetermined bit length. Simultaneously, a carrier-sense-signal, which alerts the coprocessor that serial data is ready to be received, is modified by a carrier-sense-signal regeneration circuit. If the carrier-sense-signal is detected true by the regeneration circuit for a number of clock cycles equal to the number of bits in the data-shift register, then the carrier-sense-signal is delivered to the coprocessor and the data in the data-shift register is received by the coprocessor. Once the carrier-sense signal goes false, the regeneration circuit continues to deliver the carrier-sense-signal until the data-shift register empties.