Abstract: A single supply, TTL-compatible, class A-B signal buffer architecture comprises a multistage emitter-follower transistor circuit that is coupled between an input terminal and an output terminal capable of sinking and sourcing current to TTL specifications. A reference emitter-follower transistor stage is coupled in parallel with one of the emitter-follower transistor stages of the multistage emitter-follower transistor circuit, and a common emitter, current control transistor stage has its emitter-collector path coupled between the output terminal and ground for controlling the operation of the multistage emitter-follower transistor circuit. A differential amplifier stage, one arm of which is used to controllably forward bias the base-emitter junction of the current control transistor, has a first input coupled to the reference emitter-follower transistor stage and a second input coupled to the one emitter-follower transistor stage of the multistage emitter-follower transistor circuit.