Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to improve webservers using dynamic load balancers. An example method includes identifying a first and second data object type associated with media and with first and second data objects of the media. The example method also includes enqueuing first and second event data associated with the first and second data object in a first and second queue in first circuitry in a die of programmable circuitry. The example method further includes dequeuing the first and second event data into a third and fourth queue associated with a first and second core of the programmable circuitry, the first circuitry separate from the first core and the second core. The example method additionally includes causing the first and second core to execute a first and second computing operation based on the first and second event data in the third and fourth queues.

Abstract: Systems, apparatus, articles of manufacture, and methods are disclosed for wireless network optimization. An example apparatus includes interface circuitry, machine readable instructions, and programmable circuitry. The example interface circuitry is to obtain multi-access wireless data from a wireless device associated with a network, the multi-access wireless data associated with an operation of at least one of the wireless device or infrastructure of the network. Additionally, the example programmable circuitry is to utilize the machine readable instructions to compute, in substantially real time relative to the operation, a measurement based on the multi-access wireless data. The example programmable circuitry is also to determine, in substantially real time relative to the operation, a change to a configuration of at least one of the wireless device or a virtual radio based on the measurement, the virtual radio associated with the network.

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed for private network mobility management. An example private network in a box includes interface circuitry to communicate with multi-access terrestrial network (TN) nodes and non-terrestrial network (NTN) nodes, machine readable instructions, and programmable circuitry. The example programmable circuitry is to generate a first mesh associated with a geographical area of the private network and a second mesh associated with the geographical area. The example programmable circuitry is also to initiate at least one of the multi-access TN nodes in alignment with the first mesh and at least one of the NTN nodes in alignment with the second mesh. Additionally, the example programmable circuitry is to facilitate communication associated with at least one user equipment within at least one of the first mesh or the second mesh using the private network.

Abstract: Systems, apparatus, articles of manufacture, and methods are disclosed. An example edge compute device disclosed herein includes interface circuitry, machine readable instructions, and programmable circuitry to execute the machine readable instructions to configure compute resources of the edge compute device based on a first resource demand associated with a first location of the edge compute device, detect a change in location of the edge compute device to a second location, and in response to detection of the change in location, reconfigure the compute resources of the edge compute device based on a second resource demand associated with the second location.

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed for triggerable data driven location determination. An example apparatus is to cause transmission of a sounding reference signal (SRS) configuration to a radio access network (RAN), the SRS configuration for a target device in communication with a radio unit (RU) associated with the RAN. Additionally, the example apparatus is to cause transmission of a value to cause the RAN to compute at least one set of time-of-arrival (TOA) measurements or time-difference-of-arrival (TDOA) measurements for the target device based on detection of SRS data in cellular data received by antennas of the RU from the target device, the at least set one of the TOA measurements or the TDOA measurements based on the SRS configuration. The example apparatus is to estimate a location of the target device based on the at least one set of the TOA measurements or the TDOA measurements.

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed for dynamic load balancing for multi-core computing environments. An example apparatus includes a first and a plurality of second cores of a processor, and circuitry in a die of the processor separate from the first and the second cores, the circuitry to enqueue identifiers in one or more queues in the circuitry associated with respective ones of data packets of a packet flow, allocate one or more of the second cores to dequeue first ones of the identifiers in response to a throughput parameter of the first core not satisfying a throughput threshold to cause the one or more of the second cores to execute one or more operations on first ones of the data packets, and provide the first ones to one or more data consumers to distribute the first data packets.

Abstract: Systems, methods, and apparatus for workload optimized central processing units are disclosed herein. An example apparatus includes a workload analyzer to determine an application ratio associated with the workload, the application ratio based on an operating frequency to execute the workload, a hardware configurator to configure, before execution of the workload, at least one of (i) one or more cores of the processor circuitry based on the application ratio or (ii) uncore logic of the processor circuitry based on the application ratio, and a hardware controller to initiate the execution of the workload with the at least one of the one or more cores or the uncore logic.

Abstract: Systems, apparatus, and methods to workload optimize hardware are disclosed herein. An example apparatus includes power control circuitry to determine an application ratio based on an instruction to be executed by one or more cores of a processor to execute a workload, and configure, before the execution of the workload, at least one of (i) the one or more cores of the processor based on the application ratio or (ii) uncore logic of the processor based on the application ratio, and execution circuitry to execute the workload with the at least one of the one or more cores or the uncore logic.

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed for dynamic load balancing for multi-core computing environments. An example apparatus includes a first and a plurality of second cores of a processor, and circuitry in a die of the processor separate from the first and the second cores, the circuitry to enqueue identifiers in one or more queues in the circuitry associated with respective ones of data packets of a packet flow, allocate one or more of the second cores to dequeue first ones of the identifiers in response to a throughput parameter of the first core not satisfying a throughput threshold to cause the one or more of the second cores to execute one or more operations on first ones of the data packets, and provide the first ones to one or more data consumers to distribute the first data packets.

Abstract: Systems, apparatus, articles of manufacture, and methods are disclosed for distributed and scalable high performance location and positioning. Disclosed example apparatus are to enqueue a data pointer associated with sounding reference signal (SRS) measurement data from a device into a first data queue associated with a first worker core. Disclosed example apparatus are also to generate, with the first worker core, at least one of a reception angle measurement dataset or a time-of-arrival measurement dataset based on the SRS measurement data and dequeue the data pointer associated with the at least one of the reception angle measurement dataset or the time-of-arrival measurement dataset from the first data queue into a second data queue associated with a second worker core. Disclosed example apparatus are further to determine, with the second worker core, a location of the device based on the at least one of the reception angle or time-of-arrival measurement dataset.

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed. An example apparatus includes: interface circuitry to receive a first value and a second value; selector circuitry to select a first subset of bits and a second subset of bits from the first value; multiplier circuitry to: multiply the first subset to the second value during a first compute cycle; and multiply the second subset to the second value during a second compute cycle; left shift circuitry to perform a bitwise shift with a product of the first subset and the second value during the second compute cycle; adder circuitry to add a product of the second subset and the second value to a result of the plurality of bitwise shift operations during the second compute cycle; and comparator circuitry to determine the result of the modular multiplication based on a result of the addition during the second compute cycle.

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed for hardware queue scheduling for multi-core computing environments. An example apparatus includes a first core and a second core of a processor, and circuitry in a die of the processor, at least one of the first core or the second core included in the die, the at least one of the first core or the second core separate from the circuitry, the circuitry to enqueue an identifier to a queue implemented with the circuitry, the identifier associated with a data packet, assign the identifier in the queue to a first core of the processor, and in response to an execution of an operation on the data packet with the first core, provide the identifier to the second core to cause the second core to distribute the data packet.

Abstract: A computer system may comprise a multi-chip package (MCP), which includes multi-core processor circuitry and hardware accelerator circuitry. The multi-core processor circuitry may comprise a plurality of processing cores, and the hardware accelerator circuitry may be coupled with the multi-core processor circuitry via one or more coherent interconnects and one or more non-coherent interconnects. A coherency domain of the MCP may be extended to encompass the hardware accelerator circuitry, or portions thereof An interconnect selection module may select an individual coherent interconnect or an individual non-coherent interconnect based on application requirements of an application to be executed and a workload characteristic policy. Other embodiments are described and/or claimed.

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed for dynamic load balancing for multi-core computing environments. An example apparatus includes a first and a plurality of second cores of a processor, and circuitry in a die of the processor separate from the first and the second cores, the circuitry to enqueue identifiers in one or more queues in the circuitry associated with respective ones of data packets of a packet flow, allocate one or more of the second cores to dequeue first ones of the identifiers in response to a throughput parameter of the first core not satisfying a throughput threshold to cause the one or more of the second cores to execute one or more operations on first ones of the data packets, and provide the first ones to one or more data consumers to distribute the first data packets.

Abstract: A computer system may comprise a multi-chip package (MCP), which includes multi-core processor circuitry and hardware accelerator circuitry. The multi-core processor circuitry may comprise a plurality of processing cores, and the hardware accelerator circuitry may be coupled with the multi-core processor circuitry via one or more coherent interconnects and one or more non-coherent interconnects. A coherency domain of the MCP may be extended to encompass the hardware accelerator circuitry, or portions thereof An interconnect selection module may select an individual coherent interconnect or an individual non-coherent interconnect based on application requirements of an application to be executed and a workload characteristic policy. Other embodiments are described and/or claimed.

Abstract: Disclosed herein is a three dimensional quadrupole ion trap for analyzing samples. The ion trap includes a pair of opposing end cap electrodes which define a cavity and an axis between them. The ion trap includes a ring electrode attached between the end cap electrodes and circumscribing the axis. Each of the end cap electrodes and ring electrodes are made from Molybdenum to minimize chemical reactivity and to resist thermal deformation.

Abstract: Disclosed herein is a three dimensional quadrupole ion trap for analyzing samples. The ion trap includes two spaced apart end cap electrodes being generally opposed to one another and defining a first axis between them. The ion trap includes a ring electrode between the end cap electrodes and adjacent thereto. Each of the end caps and ring electrodes are made from Molybdenum. The ion trap having a cavity defined by the end caps and ring electrodes. The ion trap including a sample injector for injecting the sample into the cavity, an rf source for filtering the ions of the sample and a DC source for selectively accelerating the filtered ions into an analyzer a cavity.