Abstract: A time division multiplex switching apparatus is provided for switching channels from any number of input data streams, each of which may have any of a plurality of data rates, to any of a plurality of output data streams, each of which may likewise have any one of a plurality of data rates. An input block 1 comprises a respective input channel for each input stream. Each channel has a variable delay circuit. The outputs of the channels are supplied to a buffer memory 3 which stores data from the input channels in a first order and reads out the data in a second order according to the channel connections required. A controller 2 controls the variable delay circuits 12–14 independently of each other so as to align the data streams from the input channels irrespective of the input stream data rates. For example, the streams may be aligned such that the zeroth channel of a predetermined frame in the input streams appear consecutively at the outputs of the input channels.

Abstract: A digital clock detector for detecting whether a digital clock, for providing an output alternating between a high value and a low value, is running or stopped, comprises:

Abstract: A time division multiplex switching apparatus is provided for switching channels from any number of input data streams, each of which may have any of a plurality of data rates, to any of a plurality of output data streams, each of which may likewise have any one of a plurality of data rates. An input block 1 comprises a respective input channel for each input stream. Each channel has a variable delay circuit. The outputs of the channels are supplied to a buffer memory 3 which stores data from the input channels in a first order and reads out the data in a second order according to the channel connections required. A controller 2 controls the variable delay circuits 12-14 independently of each other so as to align the data streams from the input channels irrespective of the input stream data rates. For example, the streams may be aligned such that the zeroth channel of a predetermined frame in the input streams appear consecutively at the outputs of the input channels.