Abstract: A semiconductor power device (100) that includes active cells in an interior region of an epitaxial layer (16) on a semiconductor substrate (12), and an edge termination structure that surrounds the cells and separates the cells from the die edge (48). A polysilicon layer (26) overlies and is electrically insulated from the epitaxial layer (16), a gate metal field plate (36) contacts the polysilicon layer (26), and a portion of the polysilicon layer (26) forms a gate for each cell. Each of the active cells also has a collector/anode terminal formed by the substrate (12), an emitter/cathode terminal formed by a well (18), emitter diffusion (20) and emitter metal (22), and a base formed by the epitaxial layer (16).

Abstract: A semiconductor power device (100) that includes a number of bipolar or FET power devices (116), an over-voltage clamp (118), and an edge termination structure (110) that separates the power devices (116) and the over-voltage clamp (118). The power devices (116) are formed in an interior region (100a) of a semiconductor substrate (128), while the over-voltage clamp (118) is formed in a peripheral region (100b) of the substrate. The over-voltage clamp (118) and the gate/base terminals of the power devices (116) are formed in a polysilicon layer (126) overlying the substrate (128), such that the over-voltage clamp (118) is connected between the anode and gate/base terminals of each power device (116) to provide over-voltage protection.