Abstract: Modeling three-dimensional objects on a computer system via a high bandwidth distributed network, facilitating the computing of intensive computer-aided design (CAD) tasks to take place on a series of servers. A multi-tiered distributed processing architecture, which separates client user interface, multiple application servers and database servers is employed, resulting in the separation of server computing and data storage from the client control device. Computing for CAD tasks is directed to the client device or to an application server, as is appropriate for the complexity of tasks being performed.

Abstract: Modeling three-dimensional objects on a computer system via a high bandwidth distributed network, facilitating the computing of intensive computer-aided design (CAD) tasks to take place on a series of servers. A multi-tiered distributed processing architecture, which separates client user interface, multiple application servers and database servers is employed, resulting in the separation of server computing and data storage from the client control device. Computing for CAD tasks is directed to the client device or to an application server, as is appropriate for the complexity of tasks being performed.

Abstract: The specification discloses a technique for suppressing the effect of noise generated during the introduction of a charge into a potential well of a charge coupled device. The technique involves detecting the voltage appearing on a floating diffused region during the introduction of the charge through the floating diffused region into the CCD potential well. An error signal is developed from the detected voltage and is subsequently utilized to extract noise from the output electrical signal of the CCD.

Abstract: The specification discloses a technique for non-destructively sampling the charge stored adjacent distributed phase electrodes in a charge coupled device. A storage capacitor is provided with a capacitance in the range of the combined capacitance of the phase electrodes. A first switch is operable during a first clock period for connecting the capacitor to a source of reference voltage. A second switch is operable during the first clock period for connecting the phase electrodes to be sampled to circuit ground. An insulated gate field effect transistor is connected with its source and drain between the phase electrodes and the second switch. The gate of the transistor is biased at a voltage level less than the reference voltage.

Abstract: The specification discloses a circuit for sampling charge stored adjacent a phase electrode in a charge coupled device and for selectively weighting the sampled charge. The circuit includes a first insulated gate field effect transistor connected at its source to one end of the phase electrode and connected at its drain to receive a clock. A predetermined first voltage is applied to the gate of the first transistor. A second insulated gate field effect transistor is connected to the other end of the phase electrode and is connected at its drain to receive a clock. A preselected second voltage is applied to the gate of the second transistor in order to control the percentage of charging current applied to the phase electrode through the second transistor. The preselected second voltage is equal to or less than the predetermined first voltage in order to maintain the clock voltage of the phase electrode at a predetermined set value.