Abstract: An anti-counterfeit label includes a label body provided thereon with a first code and a second code. The second code is superimposed on the first code. The second code is a combination of code elements of at least one color at at least one position in a region where the first code is located on the label body. An anti-counterfeit system includes a cloud platform and a mobile device. The mobile device is used to scan the image formed by the combination of the first code and second code and send it to the cloud platform. The cloud platform is used to authenticate the image, and send information that corresponds to the image to the mobile device after successful authentication. An anti-counterfeit authentication method is also provided. The label, authentication system and method provide a combination code of the first code and the second code for information authentication.

Abstract: A process for fabricating a MOSFET on an SOI substrate includes the formation of an active region (14) isolated by field isolation regions (16, 18) and by an insulating layer (12). A recess (26) is formed in the active region (14) using a masking layer (22) having an opening (24) therein. A gate dielectric layer (32) is formed in the recess (26) and a polycrystalline silicon layer (34) is deposited to overlie the masking layer (22), and to fill the recess (26). A planarization process is carried out to form a gate electrode (36) in the recess (26), and source and drain regions (40, 42) are formed in a self-aligned manner to the gate electrode (36). A channel region (44) resides intermediate to the source and drain regions (40, 42) and directly below the gate electrode (36).

Abstract: A CMOS device having reduced parasitic junction capacitance and a process for fabrication of the device. The device includes an a portion (20') of an undoped epitaxial layer (20) vertically separating source and drain regions (52 and 53, 54 and 55) from buried layers (16, 18) formed in a semiconductor substrate (12). The undoped epitaxial layer (20) reduces the junction capacitance of the source and drain regions by providing an intrinsic silicon region physically separating regions of high dopant concentration from the source and drain regions. Additionally, MOS transistors fabricated in accordance with the invention have fully self-aligned channel regions extending from the upper surface (22) of the undoped epitaxial layer (20) to the buried layers (16, 18) residing in the semiconductor substrate (12).

Abstract: An improved planarization process includes the steps of forming recessed regions (38) and elevated regions (34) in a semiconductor substrate (30). The substrate is oxidized to form an oxide liner (39) overlying the recessed regions, and a fill material (40) is deposited to overlie the substrate (30) filling the recessed regions (38). An etching process is used to remove portions of the fill material (40) and to expose portions of a first planarization layer (44) overlying the elevated regions (34) of the substrate (30). The fill material is etched and a second planarization layer (46) is deposited to overlie dielectric portions (42), and portions (44) of first planarization layer (32) exposed by the etching process. A chemical-mechanical-polishing process is then carried out to form a planar surface (47), and remaining portions of the planarization layers and fill material are removed.