Abstract: A method, an apparatus, and a computer program are provided for predicting power consumption for chip. The model for predicting power consumptions is modified so at to provide a high degree of accuracy with a minimal amount of computing time. Traditionally, when modeling a chip, a vast amount of time and computer resources were required to predict power consumption. Techniques required less time and less computer power, but the accuracy also decreased. However, by breaking down a chip into macros and developing energy rules for each macro, simple techniques can be employed to accurately predict power consumption under real world conditions with a minimal amount of time and computing power.

Abstract: A method and apparatus for adding and multiplying floating-point operands such that a fixed-size mantissa result is produced. In accordance with the present addition method, the mantissa of a first floating-point operand is shifted in accordance with relative operand exponent information. Next, the first operand mantissa is added to the second operand mantissa. The addition step includes replacing a least significant non-overlapped portion of the first operand mantissa with a randomly-generated carry-in bit. In accordance with the multiplication method, a partial product array is generated from a pair of floating-point operand mantissas. Next, prior to compressing the partial product array into a compressed mantissa result, a lower-order bit portion of the partial product array is replaced with a randomly generated carry-in value.