Abstract: Ray tracing, and more generally, graphics operations taking place in a 3-D scene, involve a plurality of constituent graphics operations. Scheduling of graphics operations for concurrent execution on a computer may increase throughput. In aspects herein, constituent graphics operations are scheduled in groups, having members selected according to disclosed aspects. Processing for specific graphics operations in a group can be deferred if all the operations in the group cannot be further tested concurrently. Graphics operations that have been deferred are recombined into two or more different groups and ultimately complete processing, through a required number of iterations of such process. In one application, the performance of the graphics operations perform a search in which respective 1:1 matches between different types of geometric shapes involved in the 3-D scene are identified.

Abstract: Systems and methods include high throughput and/or parallelized ray/geometric shape intersection testing using intersection testing resources accepting and operating with block floating point data. Block floating point data sacrifices precision of scene location in ways that maintain precision where more beneficial, and allow reduced precision where beneficial. In particular, rays, acceleration structures, and primitives can be represented in a variety of block floating point formats, such that storage requirements for storing such data can be reduced. Hardware accelerated intersection testing can be provided with reduced sized math units, with reduced routing requirements. A driver for hardware accelerators can maintain full-precision versions of rays and primitives to allow reduced communication requirements for high throughput intersection testing in loosely coupled systems. Embodiments also can include using BFP formatted data in programmable test cells or more general purpose processing elements.

Abstract: Ray tracing scenes is accomplished using a plurality of intersection testing resources coupled with a plurality of shading resources, communicative in the aggregate through links/queues. A queue from testing to shading comprises respective ray/primitive intersection indications, comprising a ray identifier. A queue from shading to testing comprises identifiers of new rays to be tested, wherein data defining the rays is separately stored in memories distributed among the intersection testing resources. Ray definition data can be retained in distributed memories until rays complete intersection testing, and be selected for testing multiple times based on ray identifier. A structure of acceleration shapes can be used. Packets of ray identifiers and shape data can be passed among the intersection testing resources, and each resource can test rays identified in the packet, and for which definition data is present in its memory.

Abstract: Devices and methods providing for a isolation connector for a generally cylindrical or frustro-cylindrical housing of an implantable intravascular medical device are described herein. The isolation connector has a generally annular exterior surface, a proximal end, and a distal end. The isolation connector includes a housing interface portion at the proximal end which is secured to a first end of the housing. The proximal end of the housing interface portion is constructed to be obverse to the first end of the housing and presents a perimeter of substantially similar size and shape to the perimeter of the first end of the housing. The isolation connector further includes a first insulator portion disposed adjacent to a distal end of the housing interface portion. The isolation connector may further include a feed-through channel constructed to traverse the proximal and distal ends of the isolation connector and is defined through the housing interface portion and the first insulator portion.

Abstract: Aspects include systems, methods, and media for implementing methods relating to increasing consistency of results during intersection testing. In an example, vertexes define edges of primitives composing a scene (e.g., triangles defining a mesh for a surface of an object in a 3-D scene). An edge can be shared between two primitives. Intersection testing algorithms can use tests involving edges to determine whether or not the ray intersects a primitive defined by those edges. In one approach, a precedence among the vertexes defining a particular edge is enforced for such intersection testing. The precedence causes an intersection tester to always test a given edge in the same orientation, regardless of which primitive defined (at least in part) by that edge is being intersection tested.

Abstract: Ray tracing scenes is accomplished using a plurality of intersection testing resources coupled with a plurality of shading resources, communicative in the aggregate through links/queues. A queue from testing to shading comprises respective ray/primitive intersection indications, comprising a ray identifier. A queue from shading to testing comprises identifiers of new rays to be tested, wherein data defining the rays is separately stored in memories distributed among the intersection testing resources. Ray definition data can be retained in distributed memories until rays complete intersection testing, and be selected for testing multiple times based on ray identifier. A structure of acceleration shapes can be used. Packets of ray identifiers and shape data can be passed among the intersection testing resources, and each resource can test rays identified in the packet, and for which definition data is present in its memory.

Abstract: Ray tracing scenes is accomplished using a plurality of intersection testing resources coupled with a plurality of shading resources, communicative in the aggregate through links/queues. A queue from testing to shading comprises respective ray/primitive intersection indications, comprising a ray identifier. A queue from shading to testing comprises identifiers of new rays to be tested, wherein data defining the rays is separately stored in memories distributed among the intersection testing resources. Ray definition data can be retained in distributed memories until rays complete intersection testing, and be selected for testing multiple times based on ray identifier. A structure of acceleration shapes can be used. Packets of ray identifiers and shape data can be passed among the intersection testing resources, and each resource can test rays identified in the packet, and for which definition data is present in its memory.

Abstract: Systems, methods, and computer readable media embodying such methods provide for allowing specification of per-ray clipping information that defines a sub-portion of a 3-D scene in which the ray should be traced. The clipping information can be specified as a clip distance from a ray origin, as an end value of a parametric ray definition, or alternatively the clipping information can be built into a definition of the ray to be traced. The clipping information can be used to check whether portions of an acceleration structure need to be traversed, as well as whether primitives should be tested for intersection. Other aspects include specifying a default object that can be returned as intersected when no primitive was intersected within the sub-portion defined for testing. Further aspects include allowing provision of flags interpretable by an intersection testing resource that control what the intersection testing resource does, and/or what information it reports after conclusion of testing of a ray.

Abstract: Ray tracing scenes is accomplished using a plurality of intersection testing resources coupled with a plurality of shading resources, communicative in the aggregate through links/queues. A queue from testing to shading comprises respective ray/primitive intersection indications, comprising a ray identifier. A queue from shading to testing comprises identifiers of new rays to be tested, wherein data defining the rays is separately stored in memories distributed among the intersection testing resources. Ray definition data can be retained in distributed memories until rays complete intersection testing, and be selected for testing multiple times based on ray identifier. A structure of acceleration shapes can be used. Packets of ray identifiers and shape data can be passed among the intersection testing resources, and each resource can test rays identified in the packet, and for which definition data is present in its memory.

Abstract: Systems and methods include high throughput and/or parallelized ray/geometric shape intersection testing using intersection testing resources accepting and operating with block floating point data. Block floating point data sacrifices precision of scene location in ways that maintain precision where more beneficial, and allow reduced precision where beneficial. In particular, rays, acceleration structures, and primitives can be represented in a variety of block floating point formats, such that storage requirements for storing such data can be reduced. Hardware accelerated intersection testing can be provided with reduced sized math units, with reduced routing requirements. A driver for hardware accelerators can maintain full-precision versions of rays and primitives to allow reduced communication requirements for high throughput intersection testing in loosely coupled systems. Embodiments also can include using BFP formatted data in programmable test cells or more general purpose processing elements.

Abstract: A memory crossbar adapted to transmit a memory transaction to a network resource. The memory crossbar includes a plurality of input ports. Each of the plurality of input ports includes a TAGS generator and a queue adapted to receive a first portion of a first memory transaction and a first portion of a second memory transaction. Each of the plurality of inputs ports also includes an arbiter coupled to the queue and adapted to independently select either the first portion of the first memory transaction or the first portion of the second memory transaction based on a priority associated with the first portion of the first memory transaction and the first portion of the second memory transaction and a multiplexer coupled to the arbiter.

Abstract: A method and system for fast video transcoding are disclosed. In one embodiment, the system comprises a processor, memory coupled to the processor, a video processor and a display. The video processor includes an input that receives MPEG-2 data; and an output that provides a bitstream to a display on a portable video device. The video processor also includes a transcoder that processes the MPEG-2 data and generates H.264 data. The H.264 data is one fourth the resolution of the MPEG-2 data.

Abstract: A modular implantable medical device having first and second component containers and a flexible connector for connecting the first and second containers. The connector can include a pair of end members and a flexible portion extending therebetween to define an internal passage between the end members. Each of the end members can include a receptacle configured to communicate with the containers. The connector further includes a conduit extending between the pair of end members in the internal passage to provide a communication path between the first and second containers such that the first and second component containers are in communication.

Abstract: A method and apparatus includes a plurality of processor groups each having a plurality of processor switch chips each having a plurality of processors and a processor crossbar, each processor connected to the processor crossbar; a plurality of switch groups each having a plurality of switch crossbar chips each having a plurality of switch groups each having a plurality of switch crossbar chips each having a plurality of switch crossbars each connected to a processor crossbar in each processor group, wherein no two switch crossbars in a switch group are connected to the same processor crossbar; a plurality of memory groups having a plurality of memory switch chips each having a plurality of memory controllers and a memory crossbar, each memory controller connected to the memory crossbar, each memory crossbar in each memory group connected to all of the switch crossbar in a corresponding one of the switch groups, wherein no two memory groups are connected to the same switch group.

Abstract: A memory crossbar adapted to transmit a memory transaction to a network resource. The memory crossbar includes a plurality of input ports. Each of the plurality of input ports includes a TAGS generator and a queue adapted to receive a first portion of a first memory transaction and a first portion of a second memory transaction. Each of the plurality of inputs ports also includes an arbiter coupled to the queue and adapted to independently select either the first portion of the first memory transaction or the first portion of the second memory transaction based on a priority associated with the first portion of the first memory transaction and the first portion of the second memory transaction and a multiplexer coupled to the arbiter.

Abstract: A method, apparatus, and computer program product includes identifying a plurality of memory transactions to be sent over a memory bus to a memory having a plurality of memory banks, each memory transaction addressed to one of the memory banks, the memory bus incapable of transmitting the plurality of memory transactions simultaneously; identifying a plurality of bank readiness signals, each bank readiness signal indicating the readiness of one of the memory banks to accept a memory transaction; and selecting one of the memory transactions for transmission over the memory bus based on the bank readiness signals.

Abstract: Methods and apparatus, including computer program products, for recording and replaying audio and video programs. A device includes a video input controller, a video output controller, a command interface, a network adapter, and control circuitry. The video input controller receives an audiovisual program. The video output controller is operable to output a video signal representing the audiovisual program. The command interface is operable to receive input requesting that the audiovisual program be recorded. The network adapter is operable to connect the device to a data communication network, where the device is addressable over the data communication network through the network adapter. The control circuitry can receive the input requesting that the audiovisual program be recorded. The control circuitry can cause the requested audiovisual program to be transmitted to a remote storage device over the data communication network through the network adapter and to be recorded at the remote storage device.

Abstract: A method and apparatus includes identifying a first portion of a first message in a first slice of a switch, the first message associated with a first priority, the first portion of the first message including a first routing portion specifying a network resource; identifying a second portion of the first message in a second slice of the switch, the second portion of the first message including the first routing portion; identifying a first portion of a second message in the first slice, the second message associated with a second priority, the first portion of the second message including a second routing portion specifying the network resource; identifying a second portion of the second message in the second slice, the second portion of the second message including the second routing portion; selecting, independently in each slice, the same one of the first and second messages based on the first and second priorities; sending the first portion of the selected message from the first slice to the network reso

Abstract: Systems and methods to implement an improved floating point adder are presented. The adder integrates adding and rounding. According to an exemplary method, of adding two floating point numbers together, a first mantissa, a second mantissa, and an input bit are added together to produce a third mantissa. The third mantissa is normalized to produce a final mantissa. The third mantissa and the final mantissa are correctly rounded as a result of the act of adding, so that the final mantissa does not require processing by a follow on rounding stage.

Abstract: A method that decodes serially received MPEG variable length codes by executing instructions in parallel. The method includes an execution unit which includes multiple pipelined functional units. The functional units execute at least two of the instructions in parallel. The instructions utilize and share general purpose. registers. The general purpose. registers store information used by at least two of the instructions.