Patents by Inventor Stephen Quay

Stephen Quay has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080072202
    Abstract: A method of determining buffer insertion locations in an integrated circuit design establishes candidate locations for inserting buffers into a net, and selects buffer insertion locations from among the candidates based on slew constraints. The selection of buffer insertion locations preferably optimizes slack and buffer cost while keeping slew from any buffered node to any sink less than a required slew rate. The slew analysis computes an output slew SL(v) of a given buffer b inserted at a node v as SL(v)=RS(b)·C(v)+KS(b), where C(v) is the downstream capacitance at v, RS(b) is the slew resistance of buffer b, and KS(b) is the intrinsic slew of buffer b. The delay through a given buffer may also be computed based on signal polarity. However, the invention still preferably uses worst-case slew resistance and intrinsic slew in considering the slew constraints.
    Type: Application
    Filed: November 29, 2007
    Publication date: March 20, 2008
    Inventors: Charles Alpert, Zhuo Li, Stephen Quay
  • Publication number: 20060156266
    Abstract: A method of estimating routing congestion between pins in a net of an integrated circuit design, by establishing one or more potential routes between the pins which pass through buckets in the net, assigning a probabilistic usage to each bucket based on any partial blockage of the wiring tracks in each bucket, and computing routing congestion for each bucket using its probabilistic usage. When the net is a two-pin net that is a part of a larger multi-pin net, and a tree is constructed to bridge the two-pin net to another pin of the multi-pin net. The routing congestion for each bucket is computed as a ratio of the bucket usage to bucket capacity. For L-shaped routes (having at least one bend in a bucket), the probabilistic usage is proportional to a scale factor a which is a ratio of a minimum number of available wiring tracks for a given route to a sum of minimum numbers of available wiring tracks for all possible routes.
    Type: Application
    Filed: January 11, 2005
    Publication date: July 13, 2006
    Inventors: Charles Alpert, Zhuo Li, Stephen Quay
  • Publication number: 20060112364
    Abstract: A method of determining buffer insertion locations in an integrated circuit design establishes candidate locations for inserting buffers into a net, and selects buffer insertion locations from among the candidates based on slew constraints. The selection of buffer insertion locations preferably optimizes slack and buffer cost while keeping slew from any buffered node to any sink less than a required slew rate. The slew analysis computes an output slew SL(v) of a given buffer b inserted at a node v as SL(v)=RS(b)·C(v)+KS(b), where C(v) is the downstream capacitance at v, RS(b) is the slew resistance of buffer b, and KS(b) is the intrinsic slew of buffer b. The delay through a given buffer may also be computed based on signal polarity. However, the invention still preferably uses worst-case slew resistance and intrinsic slew in considering the slew constraints.
    Type: Application
    Filed: November 22, 2004
    Publication date: May 25, 2006
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Charles Alpert, Zhuo Li, Stephen Quay
  • Publication number: 20050138578
    Abstract: A mechanism for constructing Steiner trees using simultaneous blockage avoidance, delay optimization, and design density management are provided. An initial tiled timing-driven Steiner tree is obtained for an integrated circuit design. The Steiner tree is broken into 2-paths for which plates are generated designated the permissible area in which a Steiner point may migrate. Each 2-path is optimized by calculating a cost for each tile in the plate as a function of an environmental cost, a tile delay cost, and a trade-off value. A minimum cost tile is then selected as the point to which the Steiner point in the 2-path, if any, is to migrate. Once each 2-path is processed in this manner, routing is performed so as to minimize the cost at the source. This process may be iteratively repeated with new trade-off values until all of the nets have zero or positive slew.
    Type: Application
    Filed: December 17, 2003
    Publication date: June 23, 2005
    Applicant: International Business Machines Corporation
    Inventors: Charles Alpert, Rama Gandham, Milos Hrkic, Stephen Quay
  • Publication number: 20050138589
    Abstract: A method, apparatus, and computer program product for performing density biased buffer insertion in an integrated circuit design are provided. A tiled Steiner tree topology map is used in which density values are associated with each tile in the map. A directed acyclic graph (DAG) is created over an initial set of potential candidate points. A subset of the candidate points is selected by associating costs with each tile, and with each path or edge, to each tile. The total costs associated with placement of a buffer at a position within each tile are calculated. The lowest cost tile is then selected as a candidate position for buffer insertion. This process is then repeated to obtain an asymmetrically distributed set of candidate buffer insertion points between a source and a sink.
    Type: Application
    Filed: December 17, 2003
    Publication date: June 23, 2005
    Applicant: International Business Machines Corporation
    Inventors: Charles Alpert, Milos Hrkic, Stephen Quay
  • Patent number: D887692
    Type: Grant
    Filed: January 23, 2018
    Date of Patent: June 23, 2020
    Assignee: SPECIALIZED BICYCLE COMPONENTS, INC.
    Inventors: Stephen Quay, Justin Tucker, Nicholas Reid Gosseen, Robert A. L. Cook