Patents by Inventor Stephen R. Breit
Stephen R. Breit has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11630937Abstract: A virtual fabrication environment for semiconductor device structures that includes the use of virtual metrology measurement data to optimize a virtual fabrication sequence is described. Further, calibration of the virtual fabrication environment is performed by comparing virtual metrology measurement data from a virtual fabrication run with a subset of measurements performed in a physical fabrication environment. Additionally, virtual experiments conducted in the virtual fabrication environment of the present invention generate multiple device structure models using ranges of process and design parameter variations for an integrated process flow and design space of interest.Type: GrantFiled: June 23, 2021Date of Patent: April 18, 2023Assignee: Coventor, Inc.Inventors: Kenneth B. Greiner, Stephen R. Breit, David M. Fried, Daniel Faken
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Publication number: 20210319162Abstract: A virtual fabrication environment for semiconductor device structures that includes the use of virtual metrology measurement data to optimize a virtual fabrication sequence is described. Further, calibration of the virtual fabrication environment is performed by comparing virtual metrology measurement data from a virtual fabrication run with a subset of measurements performed in a physical fabrication environment. Additionally, virtual experiments conducted in the virtual fabrication environment of the present invention generate multiple device structure models using ranges of process and design parameter variations for an integrated process flow and design space of interest.Type: ApplicationFiled: June 23, 2021Publication date: October 14, 2021Inventors: Kenneth B. Greiner, Stephen R. Breit, David M. Fried, Daniel Faken
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Patent number: 11074388Abstract: A virtual fabrication environment for semiconductor device structures that includes the use of virtual metrology measurement data to optimize a virtual fabrication sequence is described. Further, calibration of the virtual fabrication environment is performed by comparing virtual metrology data generated from a virtual fabrication run with a subset of measurements performed in a physical fabrication environment. Additionally, virtual experiments conducted in the virtual fabrication environment of the present invention generate multiple device structure models using ranges of process and design parameter variations for an integrated process flow and design space of interest.Type: GrantFiled: March 25, 2019Date of Patent: July 27, 2021Assignee: Coventor, Inc.Inventors: Kenneth B. Greiner, Stephen R. Breit, David M. Fried, Daniel Faken
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Patent number: 11048847Abstract: A virtual fabrication environment for semiconductor device structures that includes the use of virtual metrology measurement data to optimize a virtual fabrication sequence is described. Further, calibration of the virtual fabrication environment is performed by comparing virtual metrology data generated from a virtual fabrication run with a subset of measurements performed in a physical fabrication environment. Additionally, virtual experiments conducted in the virtual fabrication environment of the present invention generate multiple device structure models using ranges of process and design parameter variations for an integrated process flow and design space of interest.Type: GrantFiled: March 1, 2019Date of Patent: June 29, 2021Assignee: Coventor, Inc.Inventors: Kenneth B. Greiner, Daniel Faken, David M. Fried, Stephen R. Breit
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Publication number: 20190286780Abstract: A virtual fabrication environment for semiconductor device structures that includes the use of virtual metrology measurement data to optimize a virtual fabrication sequence is described. Further, calibration of the virtual fabrication environment is performed by comparing virtual metrology data generated from a virtual fabrication run with a subset of measurements performed in a physical fabrication environment. Additionally, virtual experiments conducted in the virtual fabrication environment of the present invention generate multiple device structure models using ranges of process and design parameter variations for an integrated process flow and design space of interest.Type: ApplicationFiled: March 25, 2019Publication date: September 19, 2019Inventors: Kenneth B. Greiner, Stephen R. Breit, David M. Fried, Daniel Faken
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Publication number: 20190266306Abstract: A virtual fabrication environment for semiconductor device structures that includes the use of virtual metrology measurement data to optimize a virtual fabrication sequence is described. Further, calibration of the virtual fabrication environment is performed by comparing virtual metrology data generated from a virtual fabrication run with a subset of measurements performed in a physical fabrication environment. Additionally, virtual experiments conducted in the virtual fabrication environment of the present invention generate multiple device structure models using ranges of process and design parameter variations for an integrated process flow and design space of interest.Type: ApplicationFiled: March 1, 2019Publication date: August 29, 2019Inventors: Kenneth B. Greiner, Daniel Faken, David M. Fried, Stephen R. Breit
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Patent number: 10242142Abstract: A virtual fabrication environment for semiconductor device structures that includes the use of virtual metrology measurement data to optimize a virtual fabrication sequence is described. Further, calibration of the virtual fabrication environment is performed by comparing virtual metrology data generated from a virtual fabrication run with a subset of measurements performed in a physical fabrication environment. Additionally, virtual experiments conducted in the virtual fabrication environment of the present invention generate multiple device structure models using ranges of process and design parameter variations for an integrated process flow and design space of interest.Type: GrantFiled: March 14, 2013Date of Patent: March 26, 2019Assignee: Coventor, Inc.Inventors: Kenneth B. Greiner, Stephen R. Breit, David M. Fried, Daniel Faken
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Patent number: 9317632Abstract: A virtual fabrication environment for semiconductor device structure development is discussed that enables the use of a selective epitaxy process to virtually model epitaxial growth of a crystalline material layer. The epitaxial growth occurs on a crystalline substrate surface of a virtually fabricated model device structure. A surface growth rate may be defined over possible 3D surface orientations of the virtually fabricated device structure by modeling the growth rates of the three major families of crystal planes. Growth rates along neighboring non-crystalline material may also be modeled.Type: GrantFiled: March 14, 2013Date of Patent: April 19, 2016Assignee: Coventor, Inc.Inventors: Daniel Faken, Kenneth B. Greiner, David M. Fried, Stephen R. Breit
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Patent number: 8959464Abstract: A virtual fabrication environment for semiconductor device structure development is discussed. The insertion of a multi-etch process step using material-specific behavioral parameters into a process sequence enables a multi-physics, multi-material etching process to be simulated using a suitable numerical technique. The multi-etch process step accurately and realistically captures a wide range of etch behavior and geometry to provide in a virtual fabrication system a semi-physical approach to modeling multi-material etches based on a small set of input parameters that characterize the etch behavior.Type: GrantFiled: March 14, 2013Date of Patent: February 17, 2015Assignee: Coventor, Inc.Inventors: Kenneth B. Greiner, Daniel Faken, David M. Fried, Stephen R. Breit
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Publication number: 20140282328Abstract: A virtual fabrication environment that enables 3D Design Rule Checks (DRCs) or Optical Rule Checks (ORCs) on 3D structural models of semiconductor devices to be performed is discussed. The virtual fabrication environment may perform 3D design rule checks, such as minimum line width, minimum space between features, and minimum contact area between adjacent materials, directly in 3D without making assumptions about the translation from 2D design data to a 3D structure effected by an integrated process flow for semiconductor devices. The required number of 3D design rule checks may therefore be significantly reduced from the number of design rule checks required in 2D environments. Embodiments may also perform the 3D design rule checks for a range of statistical variations in process and design parameters.Type: ApplicationFiled: March 14, 2013Publication date: September 18, 2014Inventors: David M. FRIED, Kenneth B. GREINER, Mark J. STOCK, Stephen R. BREIT
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Publication number: 20140282324Abstract: A virtual fabrication environment for semiconductor device structures that includes the use of virtual metrology measurement data to optimize a virtual fabrication sequence is described. Further, calibration of the virtual fabrication environment is performed by comparing virtual metrology data generated from a virtual fabrication run with a subset of measurements performed in a physical fabrication environment. Additionally, virtual experiments conducted in the virtual fabrication environment of the present invention generate multiple device structure models using ranges of process and design parameter variations for an integrated process flow and design space of interest.Type: ApplicationFiled: March 14, 2013Publication date: September 18, 2014Applicant: COVENTOR, INC.Inventors: Kenneth B. GREINER, Stephen R. BREIT, David M. FRIED, Daniel FAKEN
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Publication number: 20140282302Abstract: A virtual fabrication environment for semiconductor device structure development is discussed. The insertion of a multi-etch process step using material-specific behavioral parameters into a process sequence enables a multi-physics, multi-material etching process to be simulated using a suitable numerical technique. The multi-etch process step accurately and realistically captures a wide range of etch behavior and geometry to provide in a virtual fabrication system a semi-physical approach to modeling multi-material etches based on a small set of input parameters that characterize the etch behavior.Type: ApplicationFiled: March 14, 2013Publication date: September 18, 2014Inventors: Kenneth B. GREINER, Daniel FAKEN, David M. FRIED, Stephen R. BREIT
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Publication number: 20140278266Abstract: A virtual fabrication environment for semiconductor device structure development is discussed that enables the use of a selective epitaxy process to virtually model epitaxial growth of a crystalline material layer. The epitaxial growth occurs on a crystalline substrate surface of a virtually fabricated model device structure. A surface growth rate may be defined over possible 3D surface orientations of the virtually fabricated device structure by modeling the growth rates of the three major families of crystal planes. Growth rates along neighboring non-crystalline material may also be modeled.Type: ApplicationFiled: March 14, 2013Publication date: September 18, 2014Inventors: Daniel FAKEN, Kenneth B. GREINER, David M. FRIED, Stephen R. BREIT
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Patent number: 8832620Abstract: A virtual fabrication environment that enables 3D Design Rule Checks (DRCs) or Optical Rule Checks (ORCs) on 3D structural models of semiconductor devices to be performed is discussed. The virtual fabrication environment may perform 3D design rule checks, such as minimum line width, minimum space between features, and minimum contact area between adjacent materials, directly in 3D without making assumptions about the translation from 2D design data to a 3D structure effected by an integrated process flow for semiconductor devices. The required number of 3D design rule checks may therefore be significantly reduced from the number of design rule checks required in 2D environments. Embodiments may also perform the 3D design rule checks for a range of statistical variations in process and design parameters.Type: GrantFiled: March 14, 2013Date of Patent: September 9, 2014Assignee: Coventor, Inc.Inventors: David M. Fried, Kenneth B. Greiner, Mark J. Stock, Stephen R. Breit
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Patent number: 7272801Abstract: A system-level design and simulation environment utilizing a process specification tool that is programmatically integrated with the system level design and simulation environment thereby enabling the process-flexible design and simulation of Micro Electro-Mechanical Systems (MEMS) devices and other micro-fabricated devices is disclosed. The process specification tool is a software tool for specifying the details of the fabrication process and enables the separation of the process data from the system-level design and simulation environment. The process specification tool retrieves the process data, which may include both the process specification and material properties data. The separation of this process data from the system-level design and simulation environment allows the system-level model to have process-related parameters whose specification is not fixed, but rather is tied by reference to the process data.Type: GrantFiled: March 12, 2004Date of Patent: September 18, 2007Assignee: Coventor, Inc.Inventors: Mattan Kamon, Gunar Lorenz, Stephen R. Breit
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Publication number: 20040054509Abstract: A system and method of applying a conformal mesh to selected parts of a solid model produced by a Computer Aided Design (CAD) system is disclosed. A graphical view of the solid model and a first and second symbolic view of the underlying data are presented to a user. User-selected parts of the solid model from one symbolic view are placed into a number of different mesh zones (areas where meshing procedures are later performed) in the second symbolic view for later decomposition into small elements. The illustrative embodiment of the present invention programmatically determines which of the user selected parts represent adjacent parts in the solid model being analyzed. Parts that are determined to be adjacent are placed in the same mesh zone prior to the meshing operation being performed. The placing of the adjacent parts in the same mesh zone assures that a conformal mesh is generated across the adjacent parts.Type: ApplicationFiled: September 12, 2002Publication date: March 18, 2004Inventors: Stephen R. Breit, Martin Bachtold, Bilge Kaan Karamete, Anqing Xu