Abstract: An apparatus comprising a first plurality of parallel switches and a second plurality of parallel switches. The first plurality of parallel switches may be configured to control a voltage on a first output pin. The second plurality of parallel switches may be configured to control a voltage on a second output pin. The first and second pluralities of parallel switches may be configured to provide rise time control of a differential waveform and be driven by a phased data signal.

Abstract: A subsurface zener diode is formed in an N.sup.- epitaxial region formed on a P type substrate. The N.sup.- epitaxial region is isolated by a P.sup.+ isolation region. An N.sup.+ buried layer region is disposed between a portion of the N.sup.- epitaxial region and the P type substrate. A first P.sup.+ region is formed in the middle of the N.sup.- epitaxial region at the same time as the P.sup.+ isolation regions. Second and third adjacent P.sup.+ regions also are formed in the N.sup.- epitaxial region adjacent to and slightly overlapping the first P.sup.+ region, all three P.sup.+ regions terminating at the N.sup.+ buried layer. An N.sup.+ region, formed during an emitter diffusion operation, has first and second opposed edges centered within the overlapping portions of the first, second, and third P.sup.+ regions. Two other opposed edges of the N.sup.+ region extend beyond the other edges of the first P.sup.+ region, forming N.sup.+ N.sup.- contacts to the N.sup.

Abstract: A subsurface zener diode is formed in an N.sup.- epitaxial region formed on a P type substrate. The N.sup.- epitaxial region is isolated by a P.sup.+ isolation region. An N.sup.+ buried layer region is disposed between a portion of the N.sup.- epitaxial region and the P type substrate. A first P.sup.+ region is formed in the middle of the N.sup.- epitaxial region at the same time as the P.sup.+ isolation regions. Second and third adjacent P.sup.+ regions also are formed in the N.sup.- epitaxial region adjacent to and slightly overlapping the first P.sup.+ region, all three P.sup.+ regions terminating at the N.sup.+ buried layer. An N.sup.+ region, formed during an emitter diffusion operation, has first and second opposed edges centered within the overlapping portions of the first, second, and third P.sup.+ regions. Two other opposed edges of the N.sup.+ region extend beyond the other edges of the first P.sup.+ region, forming N.sup.+N.sup.- contacts to the N.sup.

Abstract: A high voltage constant current source circuit includes first transistor biased as a constant current source and a second transistor connected in series with the first transistor. The second transistor has a punch-through voltage that is substantially less than any breakdown voltage of the second transistor. The emitter of the second transistor is connected to the collector of the first transistor. The collector of the second transistor supplies the constant current, provides an increased high output impedance, and allows low voltage operation if the collector-to-emitter voltage of the second transistor is less than its punch-through voltage. If its punch-through voltage is exceeded, that punch-through voltage adds to the collector-to-emitter breakdown voltage of the first transistor, allowing high voltage operation.

Abstract: A band gap voltage reference circuit includes first and second NPN transistors coupled as differential pair having ratioed emitters, to produce an offset voltage, and third and fourth emitter-coupled PNP transistors connected as a current mirror to function as load devices for the first and second transistors. The emitters of the third and fourth transistors are coupled to a current source and also to a fifth PNP emitter follower transistor which drives the base of a sixth emitter follower transistor connected to the collector of a seventh transistor, the emitter of which is connected to a series string including first and second resistors. The emitter of the seventh transistor is coupled to the base of the first transistor and the junction between the first and second resistors is coupled to the base of the second transistor. The emitter of the sixth transistor is coupled to series connected third and fourth resistors, the junction of which is coupled to the base of the seventh transistor.