Patents by Inventor Stephen R. Fairbanks

Stephen R. Fairbanks has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11658481
    Abstract: Integrated circuits with enhanced EOS/ESD robustness and methods of designing same. One such integrated circuit includes a plurality of input/output pads, a positive voltage rail, a ground voltage rail, a collection of internal circuits representing the operational core of the integrated circuit, a plurality of input/output buffering circuits connected as inputs and outputs to the internal circuits, wherein the internal circuits and the input/output buffering circuits comprise functional devices, and a plurality of EOS/ESD protection circuits interconnected with the input/output pads to limit ESD voltage and/or shunt ESD current away from the functional devices. At least one of the EOS/ESD protection circuits is a MOSFET. The MOSFET has a source region having an accompanying ohmic contact. The MOSFET further has a rectifying junction contact in place of a drain region and accompanying ohmic contact.
    Type: Grant
    Filed: January 14, 2022
    Date of Patent: May 23, 2023
    Assignee: Amplexia, LLC
    Inventor: Stephen R. Fairbanks
  • Patent number: 11228174
    Abstract: Integrated circuits with enhanced EOS/ESD robustness and methods of designing same. One such integrated circuit includes a plurality of input/output pads, a positive voltage rail, a ground voltage rail, a collection of internal circuits representing the operational core of the integrated circuit, a plurality of input/output buffering circuits connected as inputs and outputs to the internal circuits, wherein the internal circuits and the input/output buffering circuits comprise functional devices, and a plurality of EOS/ESD protection circuits interconnected with the input/output pads to limit ESD voltage and/or shunt ESD current away from the functional devices. At least one of the EOS/ESD protection circuits is a MOSFET. The MOSFET has a source region having an accompanying ohmic contact. The MOSFET further has a rectifying junction contact in place of a drain region and accompanying ohmic contact.
    Type: Grant
    Filed: May 26, 2020
    Date of Patent: January 18, 2022
    Assignee: Silicet, LLC
    Inventor: Stephen R. Fairbanks
  • Patent number: 7908531
    Abstract: An automatic test system that can be configured to perform any of a number of test processes. The test system contains multiple functional modules that are interconnected by a network. By using software to configure data flow between functional modules, combinations of modules can be made, thereby creating virtual instruments. As test requirements change, the test system can be reconfigured to contain other virtual instruments, eliminating or reducing the need to add instruments to meet changing test requirements. To ensure adequate performance of the test system, a proposed configuration may be simulated, and if a virtual instrument does not provide a required level of performance, the test system may be reconfigured.
    Type: Grant
    Filed: September 29, 2006
    Date of Patent: March 15, 2011
    Assignee: Teradyne, Inc.
    Inventors: Stephen R. Fairbanks, Eric L. Truebenbach
  • Publication number: 20080098272
    Abstract: An automatic test system that can be configured to perform any of a number of test processes. The test system contains multiple functional modules that are interconnected by a network. By using software to configure data flow between functional modules, combinations of modules can be made, thereby creating virtual instruments. As test requirements change, the test system can be reconfigured to contain other virtual instruments, eliminating or reducing the need to add instruments to meet changing test requirements. To ensure adequate performance of the test system, a proposed configuration may be simulated, and if a virtual instrument does not provide a required level of performance, the test system may be reconfigured.
    Type: Application
    Filed: September 29, 2006
    Publication date: April 24, 2008
    Applicant: Teradyne, Inc.
    Inventors: Stephen R. Fairbanks, Eric L. Truebenbach