Abstract: A method includes obtaining behavioral source code defining logic to be performed using at least one logic device and constraints identifying data movements associated with execution of the logic. The at least one logic device contains multiple components that support at least one of: internal data movements within the at least one logic device and external data movements external to the logic device as defined by the behavioral source code and the constraints. The constraints identify characteristics of at least one of: the internal data movements and the external data movements. The method also includes automatically designing one or more data movers for use within the at least one logic device, where the one or more data movers are configured to perform at least one of the internal and external data movements in accordance with the characteristics.

Abstract: A method includes obtaining thermal information and latency information associated with multiple components of at least one semiconductor chip. The latency information identifies multiple latencies associated with multiple applications to be executed by the components of the at least one semiconductor chip. The method also includes scheduling, using a run-time scheduler on the at least one semiconductor chip, execution of the multiple applications by the components of the at least one semiconductor chip. The run-time scheduler utilizes the thermal information and the latency information along with run-time events to determine which components of the at least one semiconductor chip execute the applications over time.

Abstract: A method includes obtaining behavioral source code defining logic to be performed using at least one logic device and constraints identifying data movements associated with execution of the logic. The at least one logic device contains multiple components that support at least one of: internal data movements within the at least one logic device and external data movements external to the logic device as defined by the behavioral source code and the constraints. The constraints identify characteristics of at least one of: the internal data movements and the external data movements. The method also includes automatically designing one or more data movers for use within the at least one logic device, where the one or more data movers are configured to perform at least one of the internal and external data movements in accordance with the characteristics.

Abstract: A method includes obtaining thermal information and latency information associated with multiple components of at least one semiconductor chip. The latency information identifies multiple latencies associated with multiple applications to be executed by the components of the at least one semiconductor chip. The method also includes scheduling, using a run-time scheduler on the at least one semiconductor chip, execution of the multiple applications by the components of the at least one semiconductor chip. The run-time scheduler utilizes the thermal information and the latency information along with run-time events to determine which components of the at least one semiconductor chip execute the applications over time.

Abstract: A method includes obtaining behavioral source code defining logic to be performed using at least one logic device, hardware information associated with the at least one logic device, and constraints identifying user requirements associated with the at least one logic device. The method also includes generating a design for the at least one logic device using the behavioral source code, the hardware information, and the constraints. The design enables the at least one logic device to execute the logic while satisfying the user requirements. The design is generated using a machine learning/artificial intelligence (ML/AI) algorithm that iteratively modifies potential designs to meet the user requirements.

Abstract: A power system having a controller coupled to a power converter and configured to sense a pulsed load current and a load voltage, and configured to control the power converter such that the power converter draws a constant power from a power source to avoid disturbances in the power source while delivering the pulsed load current. The controller is configured to determine an average value of the pulsed load current and an average value of the load voltage to determine an average power delivered to the load. The controller is configured to dynamically establish the charge current to a capacitor bank as a function of the sensed instantaneous load voltage such that the power converter draws a constant power from the power source.

Abstract: In one aspect, an integrated circuit (IC) system includes a receiver IC configured to receive a first clock signal and includes a feedback circuit configured to provide a feedback signal to a driver IC. The IC system also includes the driver IC configured to receive a second clock signal and includes a waveform generator configured to provide synthesized waveforms from DC to K-band, a serializer/deserializer (SERDES) to receive data from the waveform generator and to provide the signal to the receiver IC and a phase selection circuit to provide a phase selection signal to the first integrated circuit based on the feedback signal. The phase selection signal calibrates the signal from the SERDES and provides phase correction to the SERDES.

Abstract: In one aspect, an integrated circuit (IC) system includes a receiver IC configured to receive a first clock signal and includes a feedback circuit to provide a feedback signal to a driver IC. The system also includes the driver IC configured to receive a second clock signal and includes a phase selection circuit configured to provide a phase selection signal to the receiver IC based on the feedback signal. The phase selection signal controls the data received by the receiver IC by adjusting the first clock signal.

Abstract: In one aspect, an integrated circuit (IC) system includes a receiver IC configured to receive a first clock signal and includes a feedback circuit to provide a feedback signal to a driver IC. The system also includes the driver IC configured to receive a second clock signal and includes a phase selection circuit configured to provide a phase selection signal to the receiver IC based on the feedback signal. The phase selection signal controls the data received by the receiver IC by adjusting the first clock signal.

Abstract: In one aspect, an integrated circuit (IC) system includes a receiver IC configured to receive a first clock signal and includes a feedback circuit configured to provide a feedback signal to a driver IC. The IC system also includes the driver IC configured to receive a second clock signal and includes a waveform generator configured to provide synthesized waveforms from DC to K-band, a serializer/deserializer (SERDES) to receive data from the waveform generator and to provide the signal to the receiver IC and a phase selection circuit to provide a phase selection signal to the first integrated circuit based on the feedback signal. The phase selection signal calibrates the signal from the SERDES and provides phase correction to the SERDES.

Abstract: A method for modifying an original blade supporting disc (8) which is integral with a turbine rotor (2), and which has an original outline, in order to create a modified disc (8) which has an outline different from the original outline and which provides a blade-supporting region (10) of increased size, including the steps of:machining away portions (14,16) of the original disc (8) which protrude beyond the outline of the modified disc (8);building up the original disc (8) with weld metal past the outline of the modified disc (8) at all locations (14,20) where the outline of the original disc (8), after the machining step, is enclosed by the outline of the modified disc (8); andmachining away parts of the weld metal to the outline of the modified disc (8).

Abstract: In a dynamoelectric machine rotor whose armature has circumferentially spaced teeth defining therebetween coil slots in which coils are disposed and which are closed by coil wedges provided with shoulders which engage armature tooth projections formed at the radially outer ends of the armature teeth to retain the slot wedges and the coils in the coil slots, the shoulders of the coil slots have self-lubricating material structures disposed thereon by which they are in engagement with armature tooth projections for the transmission of centrifugal forces generated by the coils and slot wedges to the armature teeth through the self-lubricating material structure thereby greatly reducing armature tooth peak stresses.