Abstract: A data bus sequencer for use by nodes coupled to a system bus for associating data transactions and address transactions on the bus. The data bus sequencer includes means for tracking address and command transactions occurring on an address bus, the means for tracking producing a sequence number tag corresponding to each address and command transaction occurring on the address bus. Means for associating data transactions with address and command transactions stores the sequence number tags corresponding to address and command transactions for which data transactions are to be initiated by the node. Further included are means for tracking data transactions occurring on a data bus, means for comparing tracked data transactions to associated data transactions, and means for initiating data transactions on the data bus in response to the comparison.

Abstract: A technique reduces the latency of inter-reference ordering between sets of memory reference operations in a multiprocessor system having a shared memory that is distributed among a plurality of processors that share a cache. According to the technique, each processor sharing a cache inherits a commit-signal that is generated by control logic of the multiprocessor system in response to a memory reference operation issued by another processor sharing that cache. The commit-signal facilitates serialization among the processors and shared memory entities of the multiprocessor system by indicating the apparent completion of the memory reference operation to those entities of the system.

Abstract: In accordance with the present invention, an apparatus includes a system bus having memory bank identification signals. Coupled to the system bus are at least two memory modules, each having at least one memory bank, and at least one commander module. The commander module contains decode logic which includes memory mapping registers associated with unique values to be driven on the memory bank identification signals. The memory banks contain compare logic including a virtual node identification register which stores a predetermined value to be compared with the value driven on the memory bank identification signals to determine if the memory bank is the target of the current transaction. Thus, memory banks need not decode the entire system bus address to determine if they are the target of the transaction which reduces the time required to complete a transaction with memory.

Abstract: A mechanism for ensuring the accurate and timely completion of atomic transactions by multiple nodes coupled to a memory via a common interconnect in a multiprocessor system includes a plurality of nodes coupled to a bus, the plurality of nodes including memory nodes, I/O nodes, and processor nodes. The memory nodes are each apportioned into a plurality of banks and together comprise the memory. Associated with each bank is a busy signal, indicating the availability of the bank of memory for transactions. A node may issue an atomic transaction to a block of memory data through the use of READ.sub.-- BANK.sub.-- LOCK and WRITE.sub.-- BANK.sub.-- UNLOCK instructions. The node executing the atomic transaction monitors the state of the busy signals of the banks, and when the bank is available, the node issues a READ.sub.-- BANK.sub.-- LOCK instruction, which sets the busy bit to indicate the unavailability of the bank. Upon the completion of the READ.sub.-- BANK.sub.-- LOCK instruction, the node issues a WRITE.

Abstract: A commander module including means for determining whether control of a system bus is required, means for requesting control of the system bus, prior to determining whether such control is required, and means, responsive to the determining means, for indicating that control of the system bus is required. A computer system including the system bus and at least two such commander modules coupled to the system bus and including means for arbitrating for control of the system bus including means for granting control of the system bus to one of the commander modules indicating that control of the system bus is required and having the highest arbitration priority among those commander modules also indicating that control of the system bus is required.

Abstract: Bus interfaces for nodes coupled to a system bus in a computer system, the system bus including an address bus and a separate data bus. System bus operations include address and command transactions and data transactions. Data transactions occur on the data bus separately and independently of the occurrence of address and command transactions on the address bus. A bus interface may include any of a commander address bus interface means for providing to an address bus address and command transactions, a responder address bus interface means for acknowledging receipt of address and command transactions via the address bus, a commander data bus interface means for controlling submission to the data bus of data transactions as a result of the occurrence of address and command transactions on the address bus, and a responder data bus interface means for transferring data on the data bus during a data transaction.

Abstract: A data bus sequencer for use by nodes coupled to a system bus for associating data transactions and address transactions on the bus. A mechanism for tracking address and command transactions occurring on the bus produces, for each address and command transaction occurring on the address bus, a corresponding sequence number tag. Those sequence number tags corresponding to address and command transactions for which data transactions are to be initiated by the node are stored by the data bus sequencer. The data bus sequencer further includes circuitry for counting the number of data transactions occurring on the data bus, comparing the counted number of data transactions to the stored sequence number tags and initiating data transactions on the data bus in response to the comparison.

Abstract: A memory system is provided which can adapt to being coupled to a bus capable of running at different clock speeds. The memory system is responsive to signals provided by a bus speed sensor for modifying the timing of row address strobe (RAS), column address strobe (CAS) and write enable (WE) signals. By modifying the timing of the RAS, CAS, and WE signals, the memory can be operated in systems capable of operating at a variety of bus speeds without suffering latency problems normally associated with changes in bus speed.

Abstract: A method and apparatus in a computer system for handling cache memory victim data for updating main memory. The invention operates in a computer system having one or more processor modules coupled to main memory by a system bus operating in accordance with a SNOOPING bus protocol. Upon a processor executing a READ of one of the cache memory addresses, cache memory data corresponding to the cache memory address being READ is transmitted into the data interface from the cache memory data storage. The cache memory data is received accumulatively by the data interface during the execution of the READ of the cache memory address information. A determination is made as to whether the cache memory data corresponding to the cache memory address being READ is a cache memory victim. If the determination establishes that it is a cache memory victim, the processor issues a command for transmitting cache memory victim data to main memory over the system bus.