Patents by Inventor Stephen R. Whiteley

Stephen R. Whiteley has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5099238
    Abstract: A parallel analog to digital converter which uses a dual-rank arrangement of flash converters. The flash converters have Josephson junctions and act as a sample and hold circuit. The dual-rank arrangement allows a smaller number of comparators to be used than in a pure parallel conversion scheme, which also makes encoding the outputs of the flash converters less complex. The analog to digital converter includes an encoder which controls its output interferometers based on the net flux generated by combinations of input currents into the encoder.
    Type: Grant
    Filed: November 17, 1989
    Date of Patent: March 24, 1992
    Assignee: Hypres Incorporated
    Inventor: Stephen R. Whiteley
  • Patent number: 4866302
    Abstract: A circuit is provided for sampling and accurately reproducing unknown signals which could be electrical, optical, x-ray, gamma ray or particle signals with picosecond resolution. The circuit comprises a superconductive sampling gate having at least two states which are distinguishable from one another and switching circuitry to switch the state of the sampling gate. The switching circuitry includes a sampling pulse source and a bias current source which are combined with the unknown signal to change the state of the monitor gate. A step generator utilizing Josephson junction technology is connected to the source of the unknown signal and sends a signal to the source of the unknown signal in order to initiate the outputting of the unknown signal and thus the sampling. Timing circuitry, also utilizing Josephson junction technology, provides an adjustable delay between the step signal generation and the sampling pulse generation.
    Type: Grant
    Filed: July 7, 1988
    Date of Patent: September 12, 1989
    Assignee: Hypres, Incorporated
    Inventors: Stephen R. Whiteley, Sadeg M. Faris
  • Patent number: 4809133
    Abstract: A monolithic chip is described which is suited for a superconductive device. The chip includes a substrate with high and low temperature region, a superconductive device formed on the low temperature region and various lines for transmitting signals between the device and the high temperature region. Various configurations are described for optional separation of the high and low temperature region as well as high and low bandwidth signal lines. Chips with various geometric substrates are also described.
    Type: Grant
    Filed: September 26, 1986
    Date of Patent: February 28, 1989
    Assignee: Hypres, Inc.
    Inventors: Sadeg M. Faris, Gert K. G. Hohenwarter, Stephen R. Whiteley
  • Patent number: 4789794
    Abstract: A circuit is provided for sampling and accurately reproducing unknown signals, which could be electrical, optical, X-ray, gamma ray or particle signals, with picosecond resolution. The circuit comprises a superconductive sampling gate having at least two states which are distinguishable from one another and switching circuitry to switch the state of the sampling gate. The switching circuitry includes a sampling pulse source and a bias current source which are combined with the unknown signal to change the state of the monitor gate. A step generator utilizing Josephson junction technology is connected to the source of the unknown signal and sends a signal to the source of the unknown signal in order to initiate the outputting of the unknown signal and thus the sampling. Timing circuitry, also utilizing Josephson junction technology, provides an adjustable delay between the step signal generation and the sampling pulse generation.
    Type: Grant
    Filed: September 26, 1986
    Date of Patent: December 6, 1988
    Assignee: Hypres Incorporated
    Inventors: Stephen R. Whiteley, Sadeg M. Faris
  • Patent number: 4622475
    Abstract: A data storage element having input and output ports isolated from a regenerative latch portion so that the data transmission path is not through the latch. The circuit arrangement provided greatly reduces the probability of a metastable occurrence and permits data acquisition at a high rate with minimal error, and thus is suitable for use in high-speed digital shift registers.
    Type: Grant
    Filed: March 5, 1984
    Date of Patent: November 11, 1986
    Assignee: Tektronix, Inc.
    Inventor: Stephen R. Whiteley