Abstract: A phantom-resource memory address mapping system reduces access latency in a memory configured as a stacked-hybrid or filly-interleaved hierarchy of memory resources. The address mapping system comprises memory access circuitry having a topology that combines an interleaved-based translation function in parallel with a stacked-based translation operation. The translation functions operate in conjunction with a phantom-resource memory mapping technique. The memory address mapping system reduces the latency incurred when accessing data in response to a memory reference address, while allowing flexibility with respect to the sizes and amounts of memory resources (e.g., modules, arrays and banks) that may be populated in a data processing system.