Patents by Inventor Stephen Robinson
Stephen Robinson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12657132Abstract: Techniques for controlling bandwidth in a core are described. An exemplary core includes a memory bandwidth monitor per thread local to the core, each thread's local bandwidth monitor to at least allocate bandwidth for memory requests originating from the thread according to a class of service level stored in a field of quality of service (QoS) model-specific register (MSR), the class of service level pointed to by a class of service field in a platform quality of service MSR; and execution resources to support execution of at least one thread of the core.Type: GrantFiled: March 27, 2021Date of Patent: June 16, 2026Assignee: Intel CorporationInventors: Vedvyas Shanbhogue, Krishnakumar Ganapathy, Venkateswara Madduri, James Allen, James Coleman, Stephen Robinson
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Patent number: 12642659Abstract: A cement restrictor inserter instrument (130) comprises an inserter (131) having a handle (132) at a proximal end, a cement restrictor attachment formation (137) at a distal end for releasably attaching a cement restrictor (150), a shaft (136) extending from the proximal end to the distal end and a stop (138) on the shaft and between the proximal end and the distal end; and a body (140) having a shape corresponding to the shape of an orthopaedic prosthetic implant, a spacer (142), a visible depth guide feature (190) and a releasable attachment mechanism by which the body is releasably attachable to the shaft, and wherein the spacer is configured to position the visible depth guide feature at a fixed position relative to the inserter when the spacer abuts the stop corresponding to a target cement restrictor position when the visible depth guide feature is aligned with a feature of a bone of a patient in which the cement restrictor is to be inserted.Type: GrantFiled: December 24, 2020Date of Patent: June 2, 2026Assignee: DEPUY IRELAND UNLIMITED COMPANY, LOUGHBEG INDUSTRIAL ESTATEInventors: Jason Naylor, Stephen Robinson, Charlie Weston, Caroline Wither
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Publication number: 20260089186Abstract: Responsive to domain name server (DNS) flood conditions being detected, a fully qualified domain name (FQDN) of each DNS query is checked against a table of legitimate FQDNs, and DNS queries having FQDNs that are verified as legitimate queries to pass to the DNS server are allowed, and DNS queries having FQDNs not verified as legitimate queries from passing to the DNS server are blocked.Type: ApplicationFiled: September 23, 2024Publication date: March 26, 2026Applicant: Fortinet, Inc.Inventors: Haibin Cao, Stephen Robinson, Yongping Yi, Yuying Han
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Patent number: 12544080Abstract: The invention relates to a surgical device for performing a controlled resection of the neck of a femur during a hip replacement procedure. The surgical device comprises a template comprising an aperture dimensioned for receiving a femoral head of the femur, and a frame comprising a resection guide for indicating a resection plane on the femoral neck. The femoral neck has a femoral neck axis. The frame is slidably connected to the template for positioning of the resection guide along the femoral neck axis while the template is mounted on the femoral head.Type: GrantFiled: April 16, 2020Date of Patent: February 10, 2026Assignee: DEPUY IRELAND UNLIMITED COMPANYInventors: Jamie Atkin, Sarah Bushell, Stephen Robinson
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Publication number: 20250053651Abstract: Systems, methods, and apparatuses relating to microarchitectural mechanisms for the prevention of side-channel attacks are disclosed herein. In one embodiment, a processor includes a core having a plurality of physical contexts to execute a plurality of threads, a plurality of structures shared by the plurality of threads, a context mapping structure to map context signatures to respective physical contexts of the plurality of physical contexts, each physical context to identify and differentiate state of the plurality of structures, and a context manager circuit to, when one or more of a plurality of fields that comprise a context signature is changed, search the context mapping structure for a match to another context signature, and when the match is found, a physical context associated with the match is set as an active physical context for the core.Type: ApplicationFiled: October 24, 2024Publication date: February 13, 2025Inventors: Robert S. Chappell, Jared W. Stark, IV, Joseph Nuzman, Stephen Robinson, Jason W. Brandt
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Publication number: 20250004768Abstract: Decoder circuitry to decode an instruction indicating a first vector register having a 128-bit lane to store a first matrix having two rows by K columns of data elements having a number of bits, a storage location having 128 bits to store a second matrix having K rows by two columns of data elements having the number of bits, and a second vector register having a 128-bit lane to store a third matrix having two rows by two columns of data elements having a greater number of bits. Execution circuitry is to perform operations for the instruction, including to generate and store a result matrix having two rows by two columns of result data elements having the greater number of bits in 128-bit lane of second vector register. The result matrix represents accumulation of the third matrix with product matrix generated from matrix multiplication using the first and second matrices.Type: ApplicationFiled: June 30, 2023Publication date: January 2, 2025Inventors: Alexander HEINECKE, Wing Shek WONG, Stephen ROBINSON, Raanan SADE, Amit GRADSTEIN, Simon RUBANOVICH, Michael ESPIG, Dan BAUM, Evangelos GEORGANAS, Dhiraj KALAMKAR
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Patent number: 12130915Abstract: Systems, methods, and apparatuses relating to microarchitectural mechanisms for the prevention of side-channel attacks are disclosed herein. In one embodiment, a processor core includes an instruction fetch circuit to fetch instructions; a branch target buffer comprising a plurality of entries that each include a thread identification (TID) and a privilege level bit; and a branch predictor, coupled to the instruction fetch circuit and the branch target buffer, to predict a target instruction corresponding to a branch instruction based on at least one entry of the plurality of entries in the branch target buffer, and cause the target instruction to be fetched by the instruction fetch circuit.Type: GrantFiled: February 1, 2022Date of Patent: October 29, 2024Assignee: Intel CORPORATIONInventors: Robert S. Chappell, Jared W. Stark, IV, Joseph Nuzman, Stephen Robinson, Jason W. Brandt
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Patent number: 12032485Abstract: Techniques to allow use of metadata in unused bits of virtual addresses are described. A processor of an aspect includes a decode circuit to decode a memory access instruction. The instruction to indicate one or more memory address operands that are to have address generation information and metadata. An execution circuit coupled with the decode circuit to generate a 64-bit virtual address based on the one or more memory address operands. The 64-bit virtual address having a bit 63, an X-bit address field starting at a bit 0 to store an address generated from the address generation information, and one or more metadata bits to store the metadata. The execution circuit also to perform a canonicality check on the 64-bit virtual address that does not fail due to non-canonical values of the metadata stored in the one or more metadata bits. Other processors, methods, systems, and instructions are disclosed.Type: GrantFiled: December 23, 2020Date of Patent: July 9, 2024Assignee: Intel CorporationInventors: Vedvyas Shanbhogue, Gilbert Neiger, Stephen Robinson, Dan Baum, Ron Gabor
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Patent number: 11795331Abstract: A curable photochromic composition can include: (a) a first component having a first compound with at least two active hydrogen-functional groups and an active hydrogen-functional group equivalent weight of at least 1000; (b) a second component having at least one of a polyisocyanate and a blocked polyisocyanate; and (c) at least one photochromic compound. The ratio of total isocyanate and blocked isocyanate group equivalents of the second component to total active hydrogen-functional group equivalents is at least 4:1.Type: GrantFiled: February 17, 2021Date of Patent: October 24, 2023Assignee: Transitions Optical, Inc.Inventors: Michael F. Haley, Linda K. Anderson, Anthony T. Gestrich, David B. Knowles, Stephen Robinson, Feng Wang, Elizabeth A. Zezinka
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Patent number: 11758291Abstract: A device and method used to image wells and other fluid-carrying tubulars having localized features of interest. The device scans large areas of the tubular first in a low-resolution mode, then identifies areas that contain those localized features with some probability. The device images the identified areas in a high-resolution mode and stores the images for further image processing. The device may comprise two sensors axially spaced-apart on the device, which sensors may be electromagnetic, acoustic, or cameras.Type: GrantFiled: September 29, 2020Date of Patent: September 12, 2023Assignee: DarkVision Technologies Inc.Inventors: Stephen Robinson, Kurt Kolb
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Publication number: 20230056410Abstract: A cement restrictor inserter instrument (130) comprises an inserter (131) having a handle (132) at a proximal end, a cement restrictor attachment formation (137) at a distal end for releasably attaching a cement restrictor (150), a shaft (136) extending from the proximal end to the distal end and a stop (138) on the shaft and between the proximal end and the distal end; and a body (140) having a shape corresponding to the shape of an orthopaedic prosthetic implant, a spacer (142), a visible depth guide feature (190) and a releasable attachment mechanism by which the body is releasably attachable to the shaft, and wherein the spacer is configured to position the visible depth guide feature at a fixed position relative to the inserter when the spacer abuts the stop corresponding to a target cement restrictor position when the visible depth guide feature is aligned with a feature of a bone of a patient in which the cement restrictor is to be inserted.Type: ApplicationFiled: December 24, 2020Publication date: February 23, 2023Inventors: Jason NAYLOR, Stephen ROBINSON, Charlie WESTON, Caroline WITHER
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Patent number: 11525027Abstract: The present invention relates to a curable photochromic composition that includes: (a) a photochromic compound; and (b) a segmented polymer that includes active hydrogen groups, at least one first segment, and at least one second segment, in which, (i) each first segment independently includes a (meth)acrylic polymer segment, and (ii) each second segment independently includes at least one of, a polycarbonate segment, a polyester segment, a polyether segment, a polyurethane segment, and combinations of two or more thereof. The curable photochromic composition further includes (c) a curing agent having reactive functional groups that are reactive with the active hydrogen groups of the segmented polymer (a), in which the curing agent includes at least one of, a polyisocyanate, a polyisothiocyanate, and an aminoplast. The present invention also relates to photochromic articles that include at least one layer formed from the curable photochromic composition of the present invention.Type: GrantFiled: August 9, 2017Date of Patent: December 13, 2022Assignee: Transitions Optical, Ltd.Inventors: Stephen Robinson, Anthony Thomas Gestrich, Michael Frank Haley, David B. Knowles, Cathy A. Taylor, Elizabeth A. Zezinka
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Patent number: 11490901Abstract: The invention provides a surgical device for performing a controlled resection of the neck of a femur during a hip replacement procedure. The surgical device comprises a body portion having: a frame comprising an aperture dimension for receipt of a femoral head of the femur to position the body portion with respect to a centre of the femoral head; a resection guide for indicating a position of a resection plane on the femoral neck, and an arm extending between the frame and the resection guide. The body portion includes a linear alignment surface for alignment with a femoral shaft axis of the femur while the frame is mounted on the anterior or posterior aspect of the femoral head.Type: GrantFiled: June 24, 2019Date of Patent: November 8, 2022Inventors: Jamie Atkin, David Beverland, Sarah Bushell, Oliver Coultrup, Graeme Dutton, Jason Naylor, Stephen Robinson
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Publication number: 20220335126Abstract: Systems, methods, and apparatuses relating to microarchitectural mechanisms for the prevention of side-channel attacks are disclosed herein. In one embodiment, a processor includes a core having a plurality of physical contexts to execute a plurality of threads, a plurality of structures shared by the plurality of threads, a context mapping structure to map context signatures to respective physical contexts of the plurality of physical contexts, each physical context to identify and differentiate state of the plurality of structures, and a context manager circuit to, when one or more of a plurality of fields that comprise a context signature is changed, search the context mapping structure for a match to another context signature, and when the match is found, a physical context associated with the match is set as an active physical context for the core.Type: ApplicationFiled: February 1, 2022Publication date: October 20, 2022Inventors: Robert S. Chappell, Jared W. Stark, IV, Joseph Nuzman, Stephen Robinson, Jason W. Brandt
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Publication number: 20220309005Abstract: Techniques for controlling bandwidth in a core are described. An exemplary core includes a memory bandwidth monitor per thread local to the core, each thread's local bandwidth monitor to at least allocate bandwidth for memory requests originating from the thread according to a class of service level stored in a field of quality of service (QoS) model-specific register (MSR), the class of service level pointed to by a class of service field in a platform quality of service MSR; and execution resources to support execution of at least one thread of the core.Type: ApplicationFiled: March 27, 2021Publication date: September 29, 2022Inventors: Vedvyas SHANBHOGUE, Krishnakumar GANAPATHY, Venkateswara MADDURI, James ALLEN, James COLEMAN, Stephen ROBINSON
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Publication number: 20220196635Abstract: An exemplary embodiment of the present disclosure provides A method and system for forming a microscale cell-laden matrix using an aqueous two-phase system (“ATPS”) comprising a mixture of a first material and a second material having a phase boundary between the first and second materials. The method can comprise mixing an enzyme with the first material, mixing a protein with the second material, and mixing a suspension comprising cells with one of the first material or the second material, wherein the enzyme, protein, and suspension comprising cells generate the cell-laden matrix and wherein the first material comprises a first polymer comprising polyethylene glycol and the second material can be a second polymer selected from the group consisting of dextran, polyvinyl pyrrolidone, polyvinyl alcohol, or ficoll.Type: ApplicationFiled: October 29, 2021Publication date: June 23, 2022Inventors: Stephen Robinson, Jonathan Chang, Shuichi Takayama
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Publication number: 20220198023Abstract: An embodiment of an apparatus includes memory to store a simulation model, a processor communicatively coupled to the memory, and logic communicatively coupled to the processor and the memory, the logic to run a simulation on the simulation model, identify one or more signals in the simulation model that contains data that should not be visible through any incidental channels, and selectively convert the identified one or more signals to an incidental-data state while the simulation runs. Other embodiments are disclosed and claimed.Type: ApplicationFiled: December 22, 2020Publication date: June 23, 2022Applicant: Intel CorporationInventors: Ashwini Gopinath, Jason Brandt, Stephen Robinson
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Publication number: 20220197822Abstract: Techniques to allow use of metadata in unused bits of virtual addresses are described. A processor of an aspect includes a decode circuit to decode a memory access instruction. The instruction to indicate one or more memory address operands that are to have address generation information and metadata. An execution circuit coupled with the decode circuit to generate a 64-bit virtual address based on the one or more memory address operands. The 64-bit virtual address having a bit 63, an X-bit address field starting at a bit 0 to store an address generated from the address generation information, and one or more metadata bits to store the metadata. The execution circuit also to perform a canonicality check on the 64-bit virtual address that does not fail due to non-canonical values of the metadata stored in the one or more metadata bits. Other processors, methods, systems, and instructions are disclosed.Type: ApplicationFiled: December 23, 2020Publication date: June 23, 2022Inventors: Vedvyas SHANBHOGUE, Gilbert NEIGER, Stephen ROBINSON, Dan BAUM, Ron GABOR
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Publication number: 20220125440Abstract: The invention relates to a surgical device for performing a controlled resection of the neck of a femur during a hip replacement procedure. The surgical device comprises a template comprising an aperture dimensioned for receiving a femoral head of the femur, and a frame comprising a resection guide for indicating a resection plane on the femoral neck. The femoral neck has a femoral neck axis. The frame is slidably connected to the template for positioning of the resection guide along the femoral neck axis while the template is mounted on the femoral head.Type: ApplicationFiled: April 16, 2020Publication date: April 28, 2022Inventors: Jamie ATKIN, Sarah BUSHELL, Stephen ROBINSON
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Patent number: D1046152Type: GrantFiled: June 29, 2022Date of Patent: October 8, 2024Assignee: DEPUY IRELAND UNLIMITED COMPANYInventors: Jamie Atkin, Lukas Wagner, Stephen Robinson, Graeme Dutton, Kevin Thompson