Abstract: A circuit responsive to a switching signal for dynamically changing the frequency source of a system clock. The circuit allows addition of new frequency sources without substantial changes to the circuit because its circuitry for detecting an inactive cycle period of the new frequency source is asynchronous (i.e. not clocked by the new frequency source).

Abstract: A clock control apparatus that stops a system clock in a high performance high speed computer a determined number of system clock cycles after the generation of the clock control signal by a digital computer. The apparatus receives a basic clock signal and the clock control signal and generates a system clock for the system. The system clock includes a normal system clock signal and at least one early system clock signal. The basic clock is provided through a delay tap generating a normal basic clock signal and at least one early basic clock signal. In addition, a control state machine receiving the normal basic clock signal and the at least one early basic clock signal and responsive to the clock control signal is provided for starting and stopping the system clock. The clock control signal is synchronized with the earliest system clock and supplied to the clock control state machine.

Abstract: Disclosed is a scan apparatus which provides an interface and control signals between a secondary computer and data locations in a host computer. The scan apparatus functions independently of the normal operation of the host computer. Scan-out is performed transparently to the operation of the host computer. The host computer is organized into a plurality of functional units. Each functional unit is constructed of circuits on semiconductor chips. The semiconductor chips are organized in blocks. In the present invention, each block within the host computer includes a multimode scan apparatus which controls the scan operations in connection with that block. The scan apparatus in each block is connected to the secondary computer by clock and scan lines. The scan apparatus on each block includes a multimode sequencer which is controlled by the secondary computer and independently of the operation of the host computer, executes the scan sequences for performing the scan operations associated with the block.

Abstract: Data processing apparatus includes a data path having a path delay, from a source latch point to a destination latch point, of greater than one clock cycle. For an n-cycle path, where the path delay is between n- 1 and n clock cycles, data is latched into the source latch point at least n clock cycles in advance of the cycle on which it is needed at the destination latch point. The data and gating signals along the data path are held glitch-free in the source latch point until after the clock cycle on which the data is used in the destination latch point.

Abstract: In a floating point arithmetic unit, high speed computation is achieved by providing logic for determining whether operands of an instruction have a predetermined condition with respect to the instruction and logic responsive thereto for bypassing selective primitive operations when such predetermined condition exists.

Abstract: An instruction execution unit receives instructions and, in turn, provides a sequence of control words to specify the sequential processing of the operand data provided with the instruction. A sequencer nominally issues a first sequence of control words corresponding to the instruction. The sequencer includes a sequence selector for selecting a second sequence of control words for issuance by the sequencer. Control logic is provided to determine from the operand data, concurrent with the issuance of at least the first issued control word, whether the operand data is ideal with respect to the instruction, where ideal is defined as the predicted nonoccurence of underflow and overflow conditions. On determining that the operand data is ideal with respect to the instruction, the sequence selector is caused to select the second sequence of control words for issuance.

Abstract: A scan apparatus provides an interface and control signals between a secondary computer and data locations in a host computer. The scan apparatus functions independently of the normal operation of the host computer. Scan-out is performed transparently to the operation of the host computer. The host computer is constructed using circuits on semiconductor chips. The semiconductor chips are organized in blocks. Chips within each block include scan apparatus which controls the scan operations in connection with that chip. The scan apparatus in each chip is connected through two I/O pins to a clock line and to a bidirectional scan data line. The scan apparatus on each chip includes a multimode sequencer so that each chip in each block can be independently performing scan sequences. The block scan apparatus and the secondary computer perform the functions of requesting a scan sequence for transmitting the scan data.

Abstract: An ancillary execution unit is interfaced to a primary execution unit of a data processing system where the ancillary unit operates faster than the primary for certain instructions and allows for bypassing the slower unit. The primary execution unit has an instruction input receiving an instruction, an operand input receiving data and an operand output transferring data from the primary execution unit to the data processing system. The ancillary execution unit obtains the instruction from the instruction input, obtains the data from the operand input, performs the function indicated by the instruction to the data, and returns data to the primary execution unit.