Patents by Inventor Stephen S. Poon
Stephen S. Poon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9400576Abstract: Displays such as organic light-emitting diode displays may be provided with touch sensing capabilities. A touch sensor may be formed from electrodes located on a thin-film encapsulation layer or one or more sides of a polarizer. A single-sided or double-sided touch sensor panel may be attached to the upper or lower surface of a polarizer. Control circuitry may be used to provide control signals to light-emitting diodes in the display using a grid of control lines. The control lines and transparent electrode structures such as indium tin oxide structures formed on a thin-film encapsulation layer or polarizer may be used as electrodes for a touch sensor. Displays may have active regions and inactive peripheral portions. The displays may have edge portions that are bent along a bend axis that is within the active region to form a borderless display. Virtual buttons may be formed on the bent edge portions.Type: GrantFiled: July 19, 2011Date of Patent: July 26, 2016Assignee: Apple Inc.Inventors: Wei Chen, Steven P. Hotelling, John Z. Zhong, Shih-Chang Chang, Stephen S. Poon
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Patent number: 9329738Abstract: Embodiments described herein generally take the form of methods and systems for identifying and/or reducing a parasitic capacitance variation in a capacitive integrated touch-sensing module that may arise from proximity to a nearby electronic display.Type: GrantFiled: September 10, 2013Date of Patent: May 3, 2016Assignee: Apple Inc.Inventors: Marduke Yousefpor, Stephen S. Poon
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Publication number: 20150333293Abstract: An electronic device may include a display having an array of organic light-emitting diodes formed on a substrate. An encapsulation layer may be formed over the array of organic light-emitting diodes to protect the organic light-emitting diodes from moisture and other contaminants. The encapsulation layer may include a transparent sheet of material interposed between upper and lower inorganic films. The reliability of the encapsulation layer is increased by dividing one or both of the inorganic films into multiple sub-layers. The sub-layers may have different densities and may be deposited in sequential steps. Additional moisture protection may be provided by forming a conformal thin-film coating over the organic light-emitting diodes. The conformal thin-film coating may be an aluminum oxide layer that is formed using atomic layer deposition techniques.Type: ApplicationFiled: May 6, 2015Publication date: November 19, 2015Inventors: Stephen S. Poon, Chih Jen Yang, Damien S. Boesch, Bhadrinarayana L. Visweswaran
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Publication number: 20150275351Abstract: An evaporation tool is provided that has an elongated evaporation source with elongated edges that run parallel to a longitudinal axis and shorter edges that run perpendicular to the longitudinal axis. The evaporation source has multiple evaporation sources formed by respective source orifices through which material is evaporated. An evaporation control structure is mounted to the evaporation source to enhance the directionality of evaporated material. A shadow mask is provided that has a rectangular frame for supporting a metal mask layer with a pattern of openings. The evaporation control structure ensures that the evaporated material from the source is evaporated towards the shadow mask. Angled walls attached to the elongated edges, a series of vertical walls that extend between the angled walls in the evaporation control structure, and aligned vertical wall extensions on the frame of the shadow mask are used to block evaporated material following angled trajectories.Type: ApplicationFiled: September 30, 2014Publication date: October 1, 2015Inventors: Jungmin Lee, Jae Won Choi, Jueng-Gil J. Lee, Stephen S. Poon, John Z. Zhong
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Patent number: 9063605Abstract: A method of fabricating a display panel from a thin substrate using a carrier substrate is disclosed. The method includes depositing a bonding agent on a first surface of the thin substrate; depositing a bonding agent on a second surface of the carrier substrate; bonding the thin substrate and the carrier substrate with the bonding agent deposited on the first surface and the second surface; performing thin film processing on a third surface of the thin substrate opposite the first surface; and separating the processed thin substrate from the carrier substrate. The thin substrate has a thickness less than a required thickness for sustaining thin film processing while a thickness of the bonded thin substrate and the carrier substrates is greater than or equal to that the required thickness.Type: GrantFiled: September 15, 2011Date of Patent: June 23, 2015Assignee: Apple Inc.Inventors: Casey J. Feinstein, John Z. Zhong, Lynn R. Youngs, Stephen S. Poon
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Publication number: 20140354586Abstract: A touch screen to reduce touch pixel coupling. In some examples, the touch screen can include a first display pixel and a second display pixel in a row of display pixels, where the first display pixel can be configurable to be decoupled from the second display pixel during at least a touch sensing phase of the touch screen. In some examples, the touch screen can include a display pixel having a first and a second transistor, where the second transistor can be electrically connected to a gate terminal of the first transistor, and can be diode-connected. In some examples, the touch screen can include two display pixels, each display pixel having two transistors, where two of the transistors can be electrically connected to a first gate line, and the remaining two transistors can be individually electrically connected to a second and third gate line, respectively.Type: ApplicationFiled: May 31, 2013Publication date: December 4, 2014Inventors: Marduke YOUSEFPOR, Taif Ahmed SYED, Ahmad AL-DAHLE, Kevin J. WHITE, Abbas JAMSHIDI-ROUDBARI, Stephen S. POON
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Publication number: 20140070225Abstract: A TFT stack for a liquid crystal display is provided. The TFT stack includes a silicon layer that includes a heavily doped region, a non-doped region, and a lightly doped region between the heavily doped region and the non-doped region. The heavily doped region is hydrogenated. The TFT stack also includes an insulation layer that includes a first portion formed over the lightly doped region and a second portion disposed over the non-doped region and a gate metal electrode layer formed over the second portion of the non-doped region. The TFT stack also includes a first dielectric layer disposed over the gate metal electrode and over the first portion of the insulation layer. The heavily doped region is hydrogenated to reduce the dependence of the capacitance between the gate metal electrode and the conductive layer Cgd upon a bias voltage being applied between the gate metal electrode and the conductive layer.Type: ApplicationFiled: September 6, 2013Publication date: March 13, 2014Applicant: Apple Inc.Inventors: Cheng-Ho Yu, Marduke Yousefpor, Yu-Cheng Chen, Stephen S. Poon, Ting-Kuo Chang, Young Bae Park
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Publication number: 20140071087Abstract: Embodiments described herein generally take the form of methods and systems for identifying and/or reducing a parasitic capacitance variation in a capacitive integrated touch-sensing module that may arise from proximity to a nearby electronic display.Type: ApplicationFiled: September 10, 2013Publication date: March 13, 2014Applicant: Apple Inc.Inventors: Marduke Yousefpor, Stephen S. Poon
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Publication number: 20130021289Abstract: Displays such as organic light-emitting diode displays may be provided with touch sensing capabilities. A touch sensor may be formed from electrodes located on a thin-film encapsulation layer or one or more sides of a polarizer. A single-sided or double-sided touch sensor panel may be attached to the upper or lower surface of a polarizer. Control circuitry may be used to provide control signals to light-emitting diodes in the display using a grid of control lines. The control lines and transparent electrode structures such as indium tin oxide structures formed on a thin-film encapsulation layer or polarizer may be used as electrodes for a touch sensor. Displays may have active regions and inactive peripheral portions. The displays may have edge portions that are bent along a bend axis that is within the active region to form a borderless display. Virtual buttons may be formed on the bent edge portions.Type: ApplicationFiled: July 19, 2011Publication date: January 24, 2013Inventors: Wei Chen, Steven P. Hotelling, John Z. Zhong, Shih-Chang Chang, Stephen S. Poon
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Publication number: 20120009703Abstract: A method of fabricating a display panel from a thin substrate using a carrier substrate is disclosed. The method includes depositing a bonding agent on a first surface of the thin substrate; depositing a bonding agent on a second surface of the carrier substrate; bonding the thin substrate and the carrier substrate with the bonding agent deposited on the first surface and the second surface; performing thin film processing on a third surface of the thin substrate opposite the first surface; and separating the processed thin substrate from the carrier substrate. The thin substrate has a thickness less than a required thickness for sustaining thin film processing while a thickness of the bonded thin substrate and the carrier substrates is greater than or equal to that the required thickness.Type: ApplicationFiled: September 15, 2011Publication date: January 12, 2012Inventors: Casey J. FEINSTEIN, John Z. Zhong, Lynn R. Youngs, Stephen S. Poon
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Patent number: 5552332Abstract: A process for the fabrication of an MOSFET device includes the formation of a buffer layer (28) overlying the surface of a semiconductor substrate (14) adjacent to a gate electrode (18). A defect compensating species is diffused through the buffer layer (28) and through a gate dielectric layer (12) to form a defect-compensating region (30) at the surface (14) of the semiconductor substrate (10). The defect-compensating region (30) in conjunction with the buffer layer (28) minimize and control the population of point defects in the channel region (22) of the semiconductor substrate (10). By controlling the population of point defects in the channel region (22), a substantially uniform doping profile is maintained in a shallow doped region (16) formed in the semiconductor substrate (10) at the substrate surface (14). The maintenance of a uniform doping profile in the shallow doped region (16) results in improved threshold voltage stability as the lateral dimension of the channel region (22) is reduced.Type: GrantFiled: June 2, 1995Date of Patent: September 3, 1996Assignee: Motorola, Inc.Inventors: Hsing-Huang Tseng, Philip J. Tobin, Paul G. Y. Tsui, Shih W. Sun, Stephen S. Poon
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Patent number: 5436488Abstract: The reliability of integrated circuits fabricated with trench isolation is improved by increasing the thickness of the gate dielectric overlying the trench corner. After the trench isolation region (40, 56) has been formed a thin layer of silicon dioxide (44) is chemically vapor deposited over the trench isolation region (44) and the adjacent active region (23). A transistor gate electrode (46) is subsequently formed over the thin layer of silicon dioxide (44). The thin layer of silicon dioxide (44) increases the thickness of the gate dielectric that lies between the transistor gate electrode (46) and the trench corner, and therefore the breakdown voltage of the gate dielectric at the trench corner is increased.Type: GrantFiled: October 31, 1994Date of Patent: July 25, 1995Assignee: Motorola Inc.Inventors: Stephen S. Poon, Hsing-Huang Tseng
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Patent number: 5387540Abstract: The reliability of integrated circuits fabricated with trench isolation is improved by increasing the thickness of the gate dielectric overlying the trench corner. After the trench isolation region (40, 56) has been formed a thin layer of silicon dioxide (44) is chemically vapor deposited over the trench isolation region (44) and the adjacent active region (23). A transistor gate electrode (46) is subsequently formed over the thin layer of silicon dioxide (44). The thin layer of silicon dioxide (44) increases the thickness of the gate dielectric that lies between the transistor gate electrode (46) and the trench corner, and therefore the breakdown voltage of the gate dielectric at the trench corner is increased.Type: GrantFiled: September 30, 1993Date of Patent: February 7, 1995Assignee: Motorola Inc.Inventors: Stephen S. Poon, Hsing-Huang Tseng
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Patent number: 5328553Abstract: A planar surface (24) is obtained in a semiconductor device (10) having regions of differing material composition by means of a non-selective planarization process. The non-selective planarization process removes insulating material and conductive material at substantially the same rate. In one embodiment of the invention, stud vias (22) are formed by the removal of portions of a conductive layer (20) overlying the surface of an interlevel dielectric layer (16). Once the conductive layer (20) has been removed, the planarization process is continued and surface portions of the interlevel dielectric layer (16) are also removed. Upon completion of the process a planar surface (24) is formed having regions of conductive material and insulating material.Type: GrantFiled: February 2, 1993Date of Patent: July 12, 1994Assignee: Motorola Inc.Inventor: Stephen S. Poon
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Patent number: 5324690Abstract: A non-silyated, ternary boron nitride film (18, 38) is provided for semiconductor device applications. The non-silyated, ternary boron nitride film is preferably formed by plasma-enhanced chemical vapor deposition using non-silyated compounds of boron, nitrogen, and either oxygen, germanium, germanium oxide, fluorine, or carbon. In one embodiment, boron oxynitride (BNO) is deposited in a plasma-enhanced chemical vapor deposition reactor using ammonia (NH.sub.3), diborane (B.sub.2 H.sub.6), and nitrous oxide (N.sub.2 O). The BNO film has a dielectric constant of about 3.3 and exhibits a negligible removal rate in a commercial polishing apparatus. Because of its low dielectric constant and high hardness, the ternary boron nitride film formed in accordance with the invention can be advantageously used as a polish-stop layer and as a interlevel dielectric layer in a semiconductor device.Type: GrantFiled: February 1, 1993Date of Patent: June 28, 1994Assignee: Motorola Inc.Inventors: Avgerinos V. Gelatos, Stephen S. Poon
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Patent number: 5254873Abstract: A trench structure (10) using germanium silicate. The trench structure (10) has a substrate material (12) and a hard mask material (14) that overlies the substrate material (12). An opening is formed in the hard mask material and the opening is used to form a trench (16) in the substrate material (12). The trench (16) has a sidewall portion and a bottom portion. A barrier (18 and 20) is formed overlying the bottom portion of the trench (16) and adjacent to the sidewall portion of the trench (16). A planar germanium silicate region (22) is formed overlying the barrier (18 and 20).Type: GrantFiled: October 19, 1992Date of Patent: October 19, 1993Assignee: Motorola, Inc.Inventors: Stephen S. Poon, Papu D. Maniar
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Patent number: 5190889Abstract: A trench structure (10) using germanium silicate. The trench structure (10) has a substrate material (12) and a hard mask material (14) that overlies the substrate material (12). An opening is formed in the hard mask material and the opening is used to form a trench (16) in the substrate material (12). The trench (16) has a sidewall portion and a bottom portion. A barrier (18 and 20) is formed overlying the bottom portion of the trench (16) and adjacent to the sidewall portion of the trench (16). A planar germanium silicate region (22) is formed overlying the barrier (18 and 20).Type: GrantFiled: December 9, 1991Date of Patent: March 2, 1993Assignee: Motorola, Inc.Inventors: Stephen S. Poon, Papu D. Maniar
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Patent number: 5064683Abstract: In a polish palnarization process using a polishing apparatus and an abrasive slurry, a boron nitride (BN) polish stop layer (18) is provided to increase the polish selectivity. The BN layer deposited in accordance with the invention has a hexagonal-close-pack crystal orientation and is characterized by chemical inertness and high hardness. The BN layer has a negligible polish removal rate yielding extremely high polish selectivity when used as a polish stop for polishing a number of materials commonly used in the fabrication of semiconductor devices. In accordance with the invention, a substrate (12) is provided having an uneven topography including elevated regions and recessed regions. A BN polish stop layer (18) is desposited to overlie the substrate (12) and a fill material (20, 36) which can be dielectric material or a conductive material, is deposited to overlie the BN polish stop (18) and the recessed regions of the substrate.Type: GrantFiled: October 29, 1990Date of Patent: November 12, 1991Assignee: Motorola, Inc.Inventors: Stephen S. Poon, Avgerinos V. Gelatos
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Patent number: 4978626Abstract: An LDD transistor is formed by using a process which insures that a layer of gate oxide is not inadvertently etched into and is not ruptured by static electrical charges. At least two thicknesses of gate electrode material of varying doping levels are formed over a layer of gate oxide which is above a semiconductor substrate. A chemical etch is utilized wherein by monitoring a ratio of chemical product and chemical reactant of the chemical etch reactions, specific endpoints in the etching of the gate electrode material can be easily detected. A small layer of gate electrode material is allowed to remain over the gate oxide layer during ion implanting and the formation and removal of gate sidewall spacers used in fabricating an LDD transistor. After formation of most of the LDD transistor, the remaining protective thickness of gate electrode material is removed and the exposed gate oxide layer is exposed to a final oxidizing anneal step.Type: GrantFiled: September 2, 1988Date of Patent: December 18, 1990Assignee: Motorola, Inc.Inventors: Stephen S. Poon, James R. Pfiester, Frank K. Baker, Jeffrey L. Klein
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Patent number: 4829024Abstract: A semiconductor process is provided for the formation of a very low resistance contact. After a straight wall contact is formed conventionally above a silicon substrate, a blanket metal barrier layer is deposited. A plurality of planar polysilicon layers are deposited above the metal barrier layer. The polysilicon layers have varying doping levels and are etched away. A byproduct gas of the etch reaction is monitored and the transition between polysilicon layers can be accurately noted. In this way, a layer of doped polysilicon is left above the metal barrier in the contact region. Metal may then be patterned over the entire structure to provide a low resistance reliable contact.Type: GrantFiled: September 2, 1988Date of Patent: May 9, 1989Assignee: Motorola, Inc.Inventors: Jeffrey L. Klein, Stephen S. Poon, Mark S. Swenson, Sudhir K. Madan