Patents by Inventor Stephen Saddow

Stephen Saddow has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20260104451
    Abstract: Systems and methods of testing integrated circuits independent of chip package configuration include or utilize a socket configured to receive a device under test (DUT), wherein the socket includes a plurality of input pins and a plurality of output pins, and wherein the DUT includes a plurality of device pins; a wireless communication device configured to wirelessly transmit information on the DUT to a server device operating a machine learning (ML) model, and wirelessly receive response data generated by the ML model from the server device, the response data including at least one of a pin configuration information of the DUT or a timing configuration information of the DUT; and a switch array configured to route respective ones of the plurality of device pins to corresponding ones of the plurality of output pins based on the response data.
    Type: Application
    Filed: December 16, 2025
    Publication date: April 16, 2026
    Inventors: Stephen SADDOW, Cong XU, Feng YU, Liwei XU, Yunghsiao CHUNG
  • Patent number: 12498416
    Abstract: Systems and methods of testing integrated circuits independent of chip package configuration include or utilize a socket configured to receive a device under test (DUT), wherein the socket includes a plurality of input pins and a plurality of output pins, and wherein the DUT includes a plurality of device pins; a wireless communication device configured to wirelessly transmit information on the DUT to a server device operating a machine learning (ML) model, and wirelessly receive response data generated by the ML model from the server device, the response data including at least one of a pin configuration information of the DUT or a timing configuration information of the DUT; and a switch array configured to route respective ones of the plurality of device pins to corresponding ones of the plurality of output pins based on the response data.
    Type: Grant
    Filed: October 26, 2023
    Date of Patent: December 16, 2025
    Assignees: UNIVERSITY OF SOUTH FLORIDA, GLOBAL ETS, LLC
    Inventors: Stephen Saddow, Cong Xu, Feng Yu, Liwei Xu, Yunghsiao Chung
  • Publication number: 20250251445
    Abstract: Systems and methods of testing integrated circuits independent of chip package configuration include or utilize a socket configured to receive a device under test (DUT), wherein the socket includes a plurality of input pins and a plurality of output pins, and wherein the DUT includes a plurality of device pins; a wireless communication device configured to wirelessly transmit information on the DUT to a server device operating a machine learning (ML) model, and wirelessly receive response data generated by the ML model from the server device, the response data including at least one of a pin configuration information of the DUT or a timing configuration information of the DUT; and a switch array configured to route respective ones of the plurality of device pins to corresponding ones of the plurality of output pins based on the response data.
    Type: Application
    Filed: October 26, 2023
    Publication date: August 7, 2025
    Inventors: Stephen SADDOW, Cong XU, Feng YU, Liwei XU, Yunghsiao CHUNG
  • Patent number: 6579359
    Abstract: A method is disclosed for fabricating monocrystal material with the bandgap width exceeding 1.8 eV. The method comprises the steps of processing a monocrystal semiconductor wafer to develop a porous layer through electrolytic treatment of the wafer at direct current under UV-illumination, and epitaxially growing a monocrystal layer on said porous layer. Growth on porous layer produces semiconductor material with reduced stress and better characteristics than with the same material grown on non-porous layers and substrates. Also, semiconductor device structure comprising at least one layer of porous group III material is included.
    Type: Grant
    Filed: June 2, 2000
    Date of Patent: June 17, 2003
    Assignee: Technologies and Devices International, Inc.
    Inventors: Marina Mynbaeva, Denis Tsvetkov, Vladimir Dmitriev, Alexander Lebedev, Nataliya Savkina, Alexander Syrkin, Stephen Saddow, Karim Mynbaev