Abstract: A power supply system includes a power supply coupled to a load via a main power rail, and a switch coupled between the power supply and the load on an auxiliary power rail. A controller controls the switch to couple the auxiliary power rail to the load in response to a startup command, and the controller controls the switch to uncouple the load from the auxiliary power rail in response to a shut down command and a low power mode being enabled.

Abstract: A power detection and indication circuit device includes a processor, a signal conditioning circuit coupled to the processor and an indicator coupled to the signal conditioning circuit. The power detection and indication circuit performs a test to determine the presence of a switch coupled to the processor through the conditioning circuit. In response to determining that the switch is coupled to the processor through the conditioning circuit, the power detection and indication circuit performs a test to determine a status of the switch and provides an indication of the status of the switch using the indicator.

Abstract: A power supply system includes a power supply coupled to a load via a main power rail, and a switch coupled between the power supply and the load on an auxiliary power rail. A controller controls the switch to couple the auxiliary power rail to the load in response to a startup command, and the controller controls the switch to uncouple the load from the auxiliary power rail in response to a shut down command and a low power mode being enabled.

Abstract: A power detection and indication circuit device includes a processor, a signal conditioning circuit coupled to the processor and an indicator coupled to the signal conditioning circuit. The power detection and indication circuit performs a test to determine the presence of a switch coupled to the processor through the conditioning circuit. In response to determining that the switch is coupled to the processor through the conditioning circuit, the power detection and indication circuit performs a test to determine a status of the switch and provides an indication of the status of the switch using the indicator.

Abstract: A memory 700 having an array 701 of rows and columns of dynamic memory cells 301, cells 301 of each row coupled to a refresh wordline 303a and an access wordline 303b and cells 301 of each column coupled to a refresh bitline 302a and an access bitline 302b. Refresh circuitry 711, 712, refreshes selected rows of cells corresponding to a refresh wordline 303a and a corresponding one refresh bitline 302a. Access circuitry accesses selected cells of a selected row using corresponding access wordline 303b and corresponding one of the access bitlines 302b. The access circuitry includes a new address detector of 709 for detecting receipt of a new address of said memory, a row decoder 702 for selecting access wordline in response to receipt of the new address and access sense amplifiers 703 and an access column decoder 704 accesses at least one cell along the selected wordline 303b using the corresponding access bitline 302b.