Patents by Inventor Stephen St. Onge
Stephen St. Onge has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20140033149Abstract: Systems and methods are provided for capturing mutual coupling effects between an integrated circuit chip and chip package using electronic design automation (EDA) tools. Specifically, a method is provided that is implemented in a computer infrastructure for designing an integrated circuit chip. The method includes compiling process technology parameters that describe electrical behavior for a chip-package coupling and a package of the integrated circuit chip. The method also includes generating a parasitic technology file to include the compiled process technology parameters.Type: ApplicationFiled: July 30, 2012Publication date: January 30, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Robert A. Groves, Wan Ni, Stephen A. St. Onge, Jiansheng Xu
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Patent number: 8640077Abstract: Systems and methods are provided for capturing mutual coupling effects between an integrated circuit chip and chip package using electronic design automation (EDA) tools. Specifically, a method is provided that is implemented in a computer infrastructure for designing an integrated circuit chip. The method includes compiling process technology parameters that describe electrical behavior for a chip-package coupling and a package of the integrated circuit chip. The method also includes generating a parasitic technology file to include the compiled process technology parameters.Type: GrantFiled: July 30, 2012Date of Patent: January 28, 2014Assignee: International Business Machines CorporationInventors: Robert A. Groves, Wan Ni, Stephen A. St. Onge, Jiansheng Xu
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Patent number: 8466501Abstract: An asymmetric silicon-on-insulator (SOI) junction field effect transistor (JFET) and a method. The JFET includes a bottom gate on an insulator layer, a channel region on the bottom gate and, on the channel region, source/drain regions and a top gate between the source/drain regions. STIs isolate the source/drain regions from the top gate and a DTI laterally surrounds the JFET to isolate it from other devices. Non-annular well(s) are positioned adjacent to the channel region and bottom gate (e.g., a well having the same conductivity type as the top and bottom gates can be connected to the top gate and can extend down to the insulator layer, forming a gate contact on only a portion of the channel region, and/or another well having the same conductivity type as the channel and source/drain regions can extend from the source region to the insulator layer, forming a source-to-channel strap).Type: GrantFiled: May 21, 2010Date of Patent: June 18, 2013Assignee: International Business Machines CorporationInventors: Douglas B. Hershberger, Richard A. Phelps, Robert M. Rassel, Stephen A. St. Onge, Michael J. Zierak
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Publication number: 20110284930Abstract: An asymmetric silicon-on-insulator (SOI) junction field effect transistor (JFET) and a method. The JFET includes a bottom gate on an insulator layer, a channel region on the bottom gate and, on the channel region, source/drain regions and a top gate between the source/drain regions. STIs isolate the source/drain regions from the top gate and a DTI laterally surrounds the JFET to isolate it from other devices. Non-annular well(s) are positioned adjacent to the channel region and bottom gate (e.g., a well having the same conductivity type as the top and bottom gates can be connected to the top gate and can extend down to the insulator layer, forming a gate contact on only a portion of the channel region, and/or another well having the same conductivity type as the channel and source/drain regions can extend from the source region to the insulator layer, forming a source-to-channel strap).Type: ApplicationFiled: May 21, 2010Publication date: November 24, 2011Applicant: International Business Machines CorporationInventors: Douglas B. Hershberger, Richard A. Phelps, Robert M. Rassel, Stephen A. St. Onge, Michael J. Zierak
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Patent number: 8030167Abstract: Methods are disclosed for forming a varied impurity profile for a collector using scattered ions while simultaneously forming a subcollector. In one embodiment, the invention includes: providing a substrate; forming a mask layer on the substrate including a first opening having a first dimension; and substantially simultaneously forming through the first opening a first impurity region at a first depth in the substrate (subcollector) and a second impurity region at a second depth different than the first depth in the substrate. The breakdown voltage of a device can be controlled by the size of the first dimension, i.e., the distance of first opening to an active region of the device. Numerous different sized openings can be used to provide devices with different breakdown voltages using a single mask and single implant. A semiconductor device is also disclosed.Type: GrantFiled: August 15, 2007Date of Patent: October 4, 2011Assignee: International Business Machines CorporationInventors: Douglas D. Coolbaugh, Louis D. Lanzerotti, Bradley A. Orner, Jay S. Rascoe, David C. Sheridan, Stephen A. St. Onge
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Patent number: 7868423Abstract: A structure for a semiconductor device includes an isolated MOSFET (e.g., NFET) having triple-well technology adjacent to an isolated PFET which itself is adjacent to an isolated NFET. The structure includes a substrate in which is formed a deep n-band region underneath any n-wells, p-wells and p-band regions within the substrate. One p-band region is formed above the deep n-band region and underneath the isolated p-well for the isolated MOSFET, while another p-band region is formed above the deep n-band region and underneath all of the p-wells and n-wells, including those that are part of the isolated PFET and NFET devices within the substrate. The n-wells for the isolated MOSFET are connected to the deep n-band region.Type: GrantFiled: November 12, 2008Date of Patent: January 11, 2011Assignee: International Business Machines CorporationInventors: John J. Benoit, David S. Collins, Natalie B. Feilchenfeld, Michael L. Gautsch, Xuefeng Liu, Robert M. Rassel, Stephen A. St. Onge, James A. Slinkman
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Publication number: 20100117122Abstract: A structure for a semiconductor device includes an isolated MOSFET (e.g., NFET) having triple-well technology adjacent to an isolated PFET which itself is adjacent to an isolated NFET. The structure includes a substrate in which is formed a deep n-band region underneath any n-wells, p-wells and p-band regions within the substrate. One p-band region is formed above the deep n-band region and underneath the isolated p-well for the isolated MOSFET, while another p-band region is formed above the deep n-band region and underneath all of the p-wells and n-wells, including those that are part of the isolated PFET and NFET devices within the substrate. The n-wells for the isolated MOSFET are connected to the deep n-band region.Type: ApplicationFiled: November 12, 2008Publication date: May 13, 2010Inventors: John J. Benoit, David S. Collins, Natalie B. Feilchenfeld, Michael L. Gautsch, Xuefeng Liu, Robert M. Rassel, Stephen A. St Onge, James A. Slinkman
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Patent number: 7709930Abstract: Disclosed is a method of forming a semiconductor structure that includes a discontinuous non-planar sub-collector having a different polarity than the underlying substrate. In addition, this structure includes an active area (collector) above the sub-collector, a base above the active area, and an emitter above the base. The distance between the discontinuous portions of the discontinuous sub-collector tunes the performance characteristics of the semiconductor structure. The performance characteristics that are tunable include breakdown voltage, unity current gain cutoff frequency, unity power gain cutoff frequency, transit frequency, current density, capacitance range, noise injection, minority carrier injection and trigger and holding voltage.Type: GrantFiled: April 22, 2004Date of Patent: May 4, 2010Assignee: International Business Machines CorporationInventors: Andreas Stricker, David Sheridan, Jae-Sung Rieh, Gregory Freeman, Steven Voldman, Stephen A. St. Onge
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Patent number: 7701015Abstract: Disclosed is a method and structure for an integrated circuit structure that includes a plurality of complementary metal oxide semiconductor (CMOS) transistors and a plurality of vertical bipolar transistors positioned on a single substrate. The vertical bipolar transistors are taller devices than the CMOS transistors. In this structure, a passivating layer is positioned above the substrate, and between the vertical bipolar transistors and the CMOS transistors. A wiring layer is above the passivating layer. The vertical bipolar transistors are in direct contact with the wiring layer and the CMOS transistors are connected to the wiring layer by contacts extending through the passivating layer.Type: GrantFiled: December 16, 2003Date of Patent: April 20, 2010Assignee: International Business Machines CorporationInventors: Zhong-Xiang He, Bradley A. Orner, Vidhya Ramachandran, Alvin J. Joseph, Stephen A. St. Onge, Ping-Chuan Wang
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Patent number: 7550787Abstract: Methods are disclosed for forming a varied impurity profile for a collector using scattered ions while simultaneously forming a subcollector. In one embodiment, the invention includes: providing a substrate; forming a mask layer on the substrate including a first opening having a first dimension; and substantially simultaneously forming through the first opening a first impurity region at a first depth in the substrate (subcollector) and a second impurity region at a second depth different than the first depth in the substrate. The breakdown voltage of a device can be controlled by the size of the first dimension, i.e., the distance of first opening to an active region of the device. Numerous different sized openings can be used to provide devices with different breakdown voltages using a single mask and single implant. A semiconductor device is also disclosed.Type: GrantFiled: May 31, 2005Date of Patent: June 23, 2009Assignee: International Business Machines CorporationInventors: Douglas D. Coolbaugh, Louis D. Lanzerotti, Bradley A. Orner, Jay S. Rascoe, David C. Sheridan, Stephen A. St. Onge
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Publication number: 20090057815Abstract: Methods of manufacturing a semiconductor structure are disclosed including a deep trench isolation in which a channel stop is formed in the form of an embedded impurity region in the substrate prior to the deep trench etch and formation of transistor devices (FEOL processing) on the substrate. In this fashion, the FEOL processing thermal cycles can activate the impurity region. The deep trench isolations are then formed after FEOL processing. The method achieves the reduced cost of forming deep trench isolations after FEOL processing, and allows the practice of sharing of a collector level between devices to continue. The invention also includes the semiconductor structure so formed.Type: ApplicationFiled: November 3, 2008Publication date: March 5, 2009Inventors: Louis D. Lanzerotti, Stephen A. St. Onge
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Patent number: 7491614Abstract: Methods of manufacturing a semiconductor structure are disclosed including a deep trench isolation in which a channel stop is formed in the form of an embedded impurity region in the substrate prior to the deep trench etch and formation of transistor devices (FEOL processing) on the substrate. In this fashion, the FEOL processing thermal cycles can activate the impurity region. The deep trench isolations are then formed after FEOL processing. The method achieves the reduced cost of forming deep trench isolations after FEOL processing, and allows the practice of sharing of a collector level between devices to continue.Type: GrantFiled: January 13, 2005Date of Patent: February 17, 2009Assignee: International Business Machines CorporationInventors: Louis D. Lanzerotti, Stephen A. St Onge
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Publication number: 20090039522Abstract: Disclosed is a method and structure for an integrated circuit structure that includes a plurality of complementary metal oxide semiconductor (CMOS) transistors and a plurality of vertical bipolar transistors positioned on a single substrate. The vertical bipolar transistors are taller devices than the CMOS transistors. In this structure, a passivating layer is positioned above the substrate, and between the vertical bipolar transistors and the CMOS transistors. A wiring layer is above the passivating layer. The vertical bipolar transistors are in direct contact with the wiring layer and the CMOS transistors are connected to the wiring layer by contacts extending through the passivating layer.Type: ApplicationFiled: December 16, 2003Publication date: February 12, 2009Applicant: International Business CorporationInventors: Zhong-Xiang He, Bradley A. Orner, Vidhya Ramachandran, Alvin J. Joseph, Stephen A. St. Onge, Ping-Chuan Wang
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Patent number: 7479439Abstract: A semiconductor-insulator-silicide (SIS) capacitor is formed by depositing a thin silicon containing layer on a salicide mask dielectric layer, followed by lithographic patterning of the stack and metallization of the thin silicon containing layer and other exposed semiconductor portions of a semiconductor substrate. The thin silicon containing layer is fully reacted during metallization and consequently converted to a silicide alloy layer, which is a first electrode of a capacitor. The salicide mask dielectric layer is the capacitor dielectric. The second electrode of the capacitor may be a doped polycrystalline silicon containing layer, a doped single crystalline semiconductor region, or another doped polycrystalline silicon containing layer disposed on the doped polycrystalline silicon containing layer. The SIS insulator may further comprise other dielectric layers and conductive layers to increase capacitance per area.Type: GrantFiled: April 20, 2007Date of Patent: January 20, 2009Assignee: International Business Machines CorporationInventors: Douglas D. Coolbaugh, Zhong-Xiang He, Robert M. Rassel, Richard J. Rassel, Stephen A. St Onge
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Publication number: 20080258197Abstract: A semiconductor-insulator-silicide (SIS) capacitor is formed by depositing a thin silicon containing layer on a salicide mask dielectric layer, followed by lithographic patterning of the stack and metallization of the thin silicon containing layer and other exposed semiconductor portions of a semiconductor substrate. The thin silicon containing layer is fully reacted during metallization and consequently converted to a silicide alloy layer, which is a first electrode of a capacitor. The salicide mask dielectric layer is the capacitor dielectric. The second electrode of the capacitor may be a doped polycrystalline silicon containing layer, a doped single crystalline semiconductor region, or another doped polycrystalline silicon containing layer disposed on the doped polycrystalline silicon containing layer. The SIS insulator may further comprise other dielectric layers and conductive layers to increase capacitance per area.Type: ApplicationFiled: April 20, 2007Publication date: October 23, 2008Inventors: Douglas D. Coolbaugh, Zhong-Xiang He, Robert M. Rassel, Richard J. Rassel, Stephen A. St Onge
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Patent number: 7317240Abstract: A device. The device includes two bipolar transistors electrically connected to each other. Each bipolar transistor of the two bipolar transistors may include a base contact and an emitter contact surrounding the base contact, wherein the emitters contacts of the two bipolar transistor are in electrical contact with each other. A first bipolar transistor of the two bipolar transistors may have a first wiring stack and a second bipolar transistor two bipolar transistors may have a second wiring stack, wherein the second wiring stack includes at least one more wiring level than the first wiring stack.Type: GrantFiled: December 16, 2005Date of Patent: January 8, 2008Assignee: International Business Machines CorporationInventors: Michael D. Hulvey, Stephen A. St. Onge
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Publication number: 20070275534Abstract: Methods are disclosed for forming a varied impurity profile for a collector using scattered ions while simultaneously forming a subcollector. In one embodiment, the invention includes: providing a substrate; forming a mask layer on the substrate including a first opening having a first dimension; and substantially simultaneously forming through the first opening a first impurity region at a first depth in the substrate (subcollector) and a second impurity region at a second depth different than the first depth in the substrate. The breakdown voltage of a device can be controlled by the size of the first dimension, i.e., the distance of first opening to an active region of the device. Numerous different sized openings can be used to provide devices with different breakdown voltages using a single mask and single implant. A semiconductor device is also disclosed.Type: ApplicationFiled: August 15, 2007Publication date: November 29, 2007Applicant: International Business Machines CorporationInventors: Douglas Coolbaugh, Louis Lanzerotti, Bradley Orner, Jay Rascoe, David Sheridan, Stephen St. Onge
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Patent number: 7253096Abstract: A bipolar transistor with raised extrinsic base and selectable self-alignment between the extrinsic base and the emitter is disclosed. The fabrication method may include the formation of a predefined thickness of a first extrinsic base layer of polysilicon or silicon on an intrinsic base. A dielectric landing pad is then formed by lithography on the first extrinsic base layer. Next, a second extrinsic base layer of polysilicon or silicon is formed on top of the dielectric landing pad to finalize the raised extrinsic base total thickness. An emitter opening is formed using lithography and RIE, where the second extrinsic base layer is etched stopping on the dielectric landing pad. The degree of self-alignment between the emitter and the raised extrinsic base is achieved by selecting the first extrinsic base layer thickness, the dielectric landing pad width, and the spacer width.Type: GrantFiled: November 30, 2005Date of Patent: August 7, 2007Assignee: International Business Machines CorporationInventors: Marwan H. Khater, James S. Dunn, David L. Harame, Alvin J. Joseph, Qizhi Liu, Francois Pagette, Stephen A. St. Onge, Andreas D. Stricker
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Publication number: 20060270203Abstract: Methods are disclosed for forming a varied impurity profile for a collector using scattered ions while simultaneously forming a subcollector. In one embodiment, the invention includes: providing a substrate; forming a mask layer on the substrate including a first opening having a first dimension; and substantially simultaneously forming through the first opening a first impurity region at a first depth in the substrate (subcollector) and a second impurity region at a second depth different than the first depth in the substrate. The breakdown voltage of a device can be controlled by the size of the first dimension, i.e., the distance of first opening to an active region of the device. Numerous different sized openings can be used to provide devices with different breakdown voltages using a single mask and single implant. A semiconductor device is also disclosed.Type: ApplicationFiled: May 31, 2005Publication date: November 30, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Douglas Coolbaugh, Louis Lanzerotti, Bradley Orner, Jay Rascoe, David Sheridan, Stephen St. Onge
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Publication number: 20060175634Abstract: A device. The device includes two bipolar transistors electrically connected to each other. Each bipolar transistor of the two bipolar transistors may include a base contact and an emitter contact surrounding the base contact, wherein the emitters contacts of the two bipolar transistor are in electrical contact with each other. A first bipolar transistor of the two bipolar transistors may have a first wiring stack and a second bipolar transistor two bipolar transistors may have a second wiring stack, wherein the second wiring stack includes at least one more wiring level than the first wiring stack.Type: ApplicationFiled: December 16, 2005Publication date: August 10, 2006Applicant: International Business Machines CorporationInventors: Michael Hulvey, Stephen St. Onge