Patents by Inventor Stephen Sturges

Stephen Sturges has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Compressed test patterns for a field programmable gate array
    Patent number: 11193975
    Abstract: Embodiments herein relate to apparatus, systems, and methods to compress a test pattern onto a field programmable gate array to test a device under test. This may include identifying values of a plurality of drive pins for a plurality of test cycles to apply to an input of the DUT for each of the plurality of test cycles, identifying values of a plurality of compare pins for the plurality of test cycles to compare an output of the DUT, respectively, for each of the plurality of test cycles, analyzing the identified values, compressing, based on the analysis, the values of the plurality of drive pins and the plurality of compare pins, and storing the compressed values on the FPGA.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: December 7, 2021
    Assignee: Intel Corportion
    Inventors: Christopher J. Nelson, Shelby G. Rollins, Hiren V. Tilala, Matthew Hendricks, Sundar V. Pathy, Timothy J. Callahan, Jared Pager, James Neeb, Bradly Inman, Stephen Sturges
  • COMPRESSED TEST PATTERNS FOR A FIELD PROGRAMMABLE GATE ARRAY
    Publication number: 20200003836
    Abstract: Embodiments herein relate to apparatus, systems, and methods to compress a test pattern onto a field programmable gate array to test a device under test. This may include identifying values of a plurality of drive pins for a plurality of test cycles to apply to an input of the DUT for each of the plurality of test cycles, identifying values of a plurality of compare pins for the plurality of test cycles to compare an output of the DUT, respectively, for each of the plurality of test cycles, analyzing the identified values, compressing, based on the analysis, the values of the plurality of drive pins and the plurality of compare pins, and storing the compressed values on the FPGA.
    Type: Application
    Filed: June 29, 2018
    Publication date: January 2, 2020
    Inventors: Christopher J. NELSON, Shelby G. ROLLINS, Hiren V. TILALA, Matthew HENDRICKS, Sundar V. PATHY, Timothy J. CALLAHAN, Jared PAGER, James NEEB, Bradly INMAN, Stephen STURGES
  • Low cost test for IC's or electrical modules using standard reconfigurable logic devices
    Publication number: 20060100812
    Abstract: Low cost test for Integrated Circuits or electrical modules using a reconfigurable logic device is described. In one embodiment, the invention includes configuring a reconfigurable logic device to comply with input standards of a device under test, applying test signals to the device under test, detecting output results of the device under test, and analyzing the detected output results.
    Type: Application
    Filed: October 28, 2004
    Publication date: May 11, 2006
    Inventors: Stephen Sturges, Brad Inman, Robert Hash
  • Non-invasive, low cost method and apparatus for the transmission, display and detection of internal computer status
    Publication number: 20060016384
    Abstract: A method and apparatus for permitting diagnostics in a PC is described. Signals, imperceptible to a user, are transmitted through the LED used to indicate on/off power status. A small hand-held device may be used for detecting and interpreting the signals and to provide a visual indication to the user of a particular problem.
    Type: Application
    Filed: June 29, 2004
    Publication date: January 26, 2006
    Inventors: Stephen Sturges, Brad Inman