Patents by Inventor Stephen T. Chambers

Stephen T. Chambers has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080286830
    Abstract: The invention describes the use of a biomarker pentylfuran to detect bacterial and/or fungal pathogens. Pentylfuran is released from certain pathogens and detected in the headspace gas of an in vitro culture or in the breath sample of a patient. Pentylfuran is particularly useful in the detection of Aspergillus species, especially Aspergillus fumigatus which is a pathogen of humans.
    Type: Application
    Filed: April 13, 2006
    Publication date: November 20, 2008
    Inventors: Jennifer M. Scotter, Stephen T. Chambers, Mona Syhre
  • Patent number: 7135775
    Abstract: A method, apparatus, system, and machine-readable medium for an interconnect structure in a semiconductor device and its method of formation is disclosed. Embodiments comprise a carbon-doped and silicon-doped interconnect having a concentration of silicon to avoid to forming a copper silicide layer between an interconnect and a passivation layer. Some embodiments provide unexpected results in electromigration reliability in regards to activation energy and/or mean time to failure.
    Type: Grant
    Filed: November 12, 2002
    Date of Patent: November 14, 2006
    Assignee: Intel Corporation
    Inventors: Stephen T. Chambers, Valery M. Dubin, Andrew W. Ott, Christine S. Hau-Riege
  • Patent number: 6818548
    Abstract: A method of fabricating a copper-containing structure, preferably within a microelectronic device, including a rapid temperature ramp from about 20 degrees Celsius up to between about 300 and 500 degrees Celsius, preferably about 400 degrees Celsius, at a rate of between about 20 and 60 degrees Celsius per second, preferably about 40 degrees Celsius per second.
    Type: Grant
    Filed: October 29, 2002
    Date of Patent: November 16, 2004
    Assignee: Intel Corporation
    Inventors: Dan S. Lavric, Stephen T. Chambers
  • Publication number: 20040120097
    Abstract: Methods for fabricating a capacitor in a microelectronic device utilizing a sputter deposition technique for forming a capacitor dielectric material on a copper-containing plate of the capacitor. Such a sputter deposition technique can be achieved at about room temperature, which should not induce stresses on the copper-containing plate, and, thus, should not generate hillocks.
    Type: Application
    Filed: December 23, 2002
    Publication date: June 24, 2004
    Inventors: Stephen T. Chambers, John Barnak
  • Publication number: 20040087147
    Abstract: A method of fabricating a copper-containing structure, preferably within a microelectronic device, including a rapid temperature ramp from about 20 degrees Celsius up to between about 300 and 500 degrees Celsius, preferably about 400 degrees Celsius, at a rate of between about 20 and 60 degrees Celsius per second, preferably about 40 degrees Celsius per second.
    Type: Application
    Filed: October 29, 2002
    Publication date: May 6, 2004
    Inventors: Dan S. Lavric, Stephen T. Chambers
  • Publication number: 20040063295
    Abstract: A method includes forming a first damascene interconnect layer in a first dielectric. A first dielectric film is deposited on the first dielectric and on the first damascene interconnect layer. A conductor layer is deposited on the first dielectric film. The conductor layer is patterned, via a single mask, to form a first conductor and a second conductor. The first damascene interconnect level, the first dielectric film, and the first conductor form a capacitor and the second conductor forms a resistor.
    Type: Application
    Filed: September 30, 2002
    Publication date: April 1, 2004
    Applicant: Intel Corporation
    Inventors: Stephen T. Chambers, Rick Davis, Philip Yashar
  • Publication number: 20030137050
    Abstract: A method, apparatus, system, and machine-readable medium for an interconnect structure in a semiconductor device and its method of formation is disclosed. Embodiments comprise a carbon-doped and silicon-doped interconnect having a concentration of silicon to avoid to forming a copper silicide layer between an interconnect and a passivation layer. Some embodiments provide unexpected results in electromigration reliability in regards to activation energy and/or mean time to failure.
    Type: Application
    Filed: November 12, 2002
    Publication date: July 24, 2003
    Inventors: Stephen T. Chambers, Valery M. Dubin, Andrew W. Ott, Christine S. Hau-Riege
  • Patent number: 6518184
    Abstract: A method, apparatus, system, and machine-readable medium for an interconnect structure in a semiconductor device and its method of formation is disclosed. Embodiments comprise a carbon-doped and silicon-doped interconnect having a concentration of silicon to avoid to forming a copper silicide layer between an interconnect and a passivation layer. Some embodiments provide unexpected results in electromigration reliability in regards to activation energy and/or mean time to failure.
    Type: Grant
    Filed: January 18, 2002
    Date of Patent: February 11, 2003
    Assignee: Intel Corporation
    Inventors: Stephen T. Chambers, Valery M. Dubin, Andrew W. Ott, Christine S. Hau-Riege
  • Patent number: 6124180
    Abstract: A BiCMOS process where a base region is formed in a relatively highly doped n-type substrate region. Boron is implanted at two different energy levels to form the base region and a counter doped n region near the base collector junction to prevent impact ionization.
    Type: Grant
    Filed: May 24, 1993
    Date of Patent: September 26, 2000
    Assignee: Intel Corporation
    Inventors: Stephen T. Chambers, Richard G. Taylor
  • Patent number: 5629547
    Abstract: A BiCMOS process where a base region is formed in a relatively highly doped n-type substrate region. Boron is implanted at two different energy levels to form the base region and a counter doped n region near the base collector junction to prevent impact ionization.
    Type: Grant
    Filed: November 16, 1995
    Date of Patent: May 13, 1997
    Assignee: Intel Corporation
    Inventors: Stephen T. Chambers, Richard G. Taylor
  • Patent number: 5420051
    Abstract: A process of forming an emitter of a bipolar transistor is described. Dopants of a first conductivity type is implanted in the substrate to form the base. Dopants of a second conductivity type is then implanted into the base region to form a substrate emitter region. A polysilicon layer is then deposited over the substrate emitter and doped to form the doped polysilicon layer. An outdiffusion step follows to link the doped polysilicon layer to the substrate emitter.
    Type: Grant
    Filed: December 28, 1993
    Date of Patent: May 30, 1995
    Assignee: Intel Corporation
    Inventors: Mark T. Bohr, Richard G. Taylor, Stephen T. Chambers
  • Patent number: 4824767
    Abstract: A method for forming contact openings in semiconductor devices. In borosilicate glass layers deposited over the gate and drain area of a device, followed by a borophosphosilicate glass layer. After masking with photoresist and defining openings, the borophosphosilicate glass is isotropically etched to undercut the resist layer. A plasma etch is utilized to anisotropically etch the borosilicate glass layer and expose the surface of the drain area. After the photoresist is stripped away, a reflow step is employed to reduce the sharp edges of the glass layer and result in a sloped contact opening profile. Good metal coverage is achieved while maintaining isolation of the gate.
    Type: Grant
    Filed: June 2, 1987
    Date of Patent: April 25, 1989
    Assignee: Intel Corporation
    Inventors: Stephen T. Chambers, Stephen T. Luce