Patents by Inventor Stephen T. Palermo
Stephen T. Palermo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11973519Abstract: Examples described herein relate to an apparatus comprising a central processing unit (CPU) and an encoding accelerator coupled to the CPU, the encoding accelerator comprising an entropy encoder to determine normalized probability of occurrence of a symbol in a set of characters using a normalized probability approximation circuitry, wherein the normalized probability approximation circuitry is to output the normalized probability of occurrence of a symbol in a set of characters for lossless compression. In some examples, the normalized probability approximation circuitry includes a shifter, adder, subtractor, or a comparator. In some examples, the normalized probability approximation circuitry is to determine normalized probability by performance of non-power of 2 division without computation by a Floating Point Unit (FPU). In some examples, the normalized probability approximation circuitry is to round the normalized probability to a decimal.Type: GrantFiled: June 23, 2020Date of Patent: April 30, 2024Assignee: Intel CorporationInventors: Bhushan G. Parikh, Stephen T. Palermo
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Publication number: 20240111531Abstract: Methods for frequency scaling for per-core accelerator assignments and associated apparatus. A processor includes a CPU (central processing unit) having multiple cores that can be selectively configured to support frequency scaling and instruction extensions. Under this approach, some cores can be configured to support a selective set of AVX instructions (such as AVX3/5G-ISA instructions) and/or AMX instructions, while other cores are configured to not support these AVX/AMX instructions. In one aspect, the selective AVX/AMX instructions are implemented in one or more ISA extension units that are separate from the main processor core (or otherwise comprises a separate block of circuitry in a processor core) that can be selectively enabled or disabled. This enables cores having the separate unit(s) disabled to consume less power and/or operate at higher frequencies, while supporting the selective AVX/AMX instructions using other cores.Type: ApplicationFiled: September 15, 2023Publication date: April 4, 2024Inventors: Stephen T. PALERMO, Srihari MAKINENI, Shubha BOMMALINGAIAHNAPALLYA, Neelam CHANDWANI, Rany T. ELSAYED, Udayan MUKHERJEE, Lokpraveen MOSUR, Adwait PURANDARE
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Patent number: 11943280Abstract: Various systems and methods for implementing a multi-access edge computing (MEC) based system to realize 5G Network Edge and Core Service Dimensioning using Machine Learning and other Artificial Intelligence Techniques, for improved operations and usage of computing and networking resources, and are disclosed herein. In an example, processing circuitry of a compute node on a network is used to analyze execution of an application to obtain operational data. The compute node then may modularize functions of the application based on the operational data to construct modularized functions. A phase transition graph is constructed using a machine-learning based analysis, the phase transition graph representing state transitions from one modularized function to another modularized function, where the phase transition graph is used to dimension the application by distributing the modularized functions across the network.Type: GrantFiled: August 8, 2022Date of Patent: March 26, 2024Assignee: Intel CorporationInventors: Mrittika Ganguli, Stephen T. Palermo, Valerie J. Parker
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Publication number: 20240098514Abstract: Various approaches for the deployment and coordination of network operation processing, compute processing, and communications for 5G networks, including with the use of fingerprint-based vRAN cell integrity monitoring, are discussed. In an example, analyzing a state of a 5G network includes: obtaining initial fingerprint reference data of a network state between a virtualized radio access network (vRAN) node and at least one fingerprint reference unit (FRU) device wirelessly connected to the vRAN node; comparing the initial fingerprint reference data to subsequent fingerprint data of the network state between the vRAN node (e.g., operating as vRAN gNB, or as an IAB Donor or IAB Node) and the at least one FRU device to detect a changed network condition; and performing an action at the vRAN node to modify or disable a component of the 5G network, in response to detection of the changed network condition.Type: ApplicationFiled: November 20, 2023Publication date: March 21, 2024Inventors: Stephen T. Palermo, Valerie J. Parker, Vishal Gupta, Patrick L. Connor, Kevin W. Bross
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Publication number: 20240014892Abstract: Various approaches for detecting and mitigating interference in a supplemental coverage from space (SCS) networking arrangement are disclosed, using an SCS zone for a geographic area in connection with exclusion, coordination, or inclusion of SCS communications in the geographic area. In an example, an approach for dynamically mitigating interference includes: obtaining orbital position data for at least one satellite vehicle (e.g., low-earth orbit (LEO) SV), which can perform SCS network communications to a geographic area that includes a terrestrial network (e.g., 5G network); determining operational parameters to mitigate terrestrial interference of the SCS network communications in the geographic area, with the geographic area identified based on the orbital position data; and modifying operation of the SCS network communications in the geographic area, based on the determined operational parameters.Type: ApplicationFiled: September 26, 2023Publication date: January 11, 2024Inventors: Stephen T. Palermo, Valerie J' Parker
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Patent number: 11775298Abstract: Methods for frequency scaling for per-core accelerator assignments and associated apparatus. A processor includes a CPU (central processing unit) having multiple cores that can be selectively configured to support frequency scaling and instruction extensions. Under this approach, some cores can be configured to support a selective set of AVX instructions (such as AVX3/5G-ISA instructions) and/or AMX instructions, while other cores are configured to not support these AVX/AMX instructions. In one aspect, the selective AVX/AMX instructions are implemented in one or more ISA extension units that are separate from the main processor core (or otherwise comprises a separate block of circuitry in a processor core) that can be selectively enabled or disabled. This enables cores having the separate unit(s) disabled to consume less power and/or operate at higher frequencies, while supporting the selective AVX/AMX instructions using other cores.Type: GrantFiled: July 20, 2020Date of Patent: October 3, 2023Assignee: Intel CorporationInventors: Stephen T. Palermo, Srihari Makineni, Shubha Bommalingaiahnapallya, Neelam Chandwani, Rany T. Elsayed, Udayan Mukherjee, Lokpraveen Mosur, Adwait Purandare
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Publication number: 20230239740Abstract: Various approaches for the deployment and coordination of terrestrial cellular (e.g., 5G) network exclusion or mitigation zone, for the dynamic deployment of radio frequency blocking for in-motion aerial devices are described. Approaches are also described for a space-based non-terrestrial network exclusion or mitigation zone, including for maintenance or multi-constellation/multi-orbit coordination. The calculation, distribution, deployment and use of exclusion and inclusion zones are described for coordination with such a terrestrial cellular network or non-terrestrial satellite network.Type: ApplicationFiled: March 16, 2023Publication date: July 27, 2023Inventors: Stephen T. Palermo, Valerie J. Parker, Jason K. Smith
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Patent number: 11711267Abstract: Various systems and methods for implementing an edge computing system to realize 5G network slices with blockchain traceability for informed 5G service supply chain are disclosed. A system configured to track network slicing operations includes memory and processing circuitry configured to select a network slice instance (NSI) from a plurality of available NSIs based on an NSI type specified by a client node. The available NSIs uses virtualized network resources of a first network resource provider. The client node is associated with the selected NSI. The utilization of the network resources by the plurality of available NSIs is determined using an artificial intelligence (AI)-based network inferencing function. A ledger entry of associating the selected NSI with the client node is recorded in a distributed ledger, which further includes a second ledger entry indicating allocations of resource subsets to each of the NSIs based on the utilization.Type: GrantFiled: February 24, 2020Date of Patent: July 25, 2023Assignee: Intel CorporationInventors: Valerie J. Parker, Neal Conrad Oliver, Stephen T. Palermo, Hari K. Tadepalli
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Publication number: 20230208510Abstract: Various approaches for the deployment and coordination of network operation processing, compute processing, and inter-satellite communication coordination, within one or multiple satellite non-terrestrial networks, are discussed. Among other examples, a data center located at one or more satellites operating in a middle Earth orbit (MEO) plane, geosynchronous orbit (GEO) plane, or high-Earth elliptical orbit (HEO) plane, may be used to provide network and data processing operations for a low-Earth orbit (LEO) constellation.Type: ApplicationFiled: February 17, 2023Publication date: June 29, 2023Inventors: Stephen T. Palermo, Valerie J. Parker, Udayan Mukherjee
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Publication number: 20230156826Abstract: Various approaches for the integration and use of edge computing operations in satellite communication environments are discussed herein. For example, connectivity and computing approaches are discussed with reference to: identifying satellite coverage and compute operations available in low earth orbit (LEO) satellites, establishing connection streams via LEO satellite networks, identifying and implementing geofences for LEO satellites, coordinating and planning data transfers across ephemeral satellite connected devices, service orchestration via LEO satellites based on data cost, handover of compute and data operations in LEO satellite networks, and managing packet processing, among other aspects.Type: ApplicationFiled: December 24, 2020Publication date: May 18, 2023Inventors: Stephen T. Palermo, Francesc Guim Bernat, Marcos E. Carranza, Kshitij Arun Doshi, Cesar Martinez-Spessot, Thijs Metsch, Ned M. Smith, Srikathyayani Srikanteswara, Timothy Verrall, Rita H. Wouhaybi, Yi Zhang, Weiqiang MA, Atul Kwatra
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Patent number: 11650851Abstract: Methods, apparatus, systems and machine-readable storage media of an edge computing device using an edge server CPU with dynamic deterministic scaling is disclosed. A processing circuitry arrangement includes processing circuitry with processor cores operating at a center base frequency and memory. The memory includes instructions configuring the processing circuitry to configure a first set of the processor cores of the CPU to switch the operating at the center base frequency to operating at a first modified base frequency, and a second set of the processor cores to switch the operating at the center base frequency to operating at a second modified base frequency. A same processor core within the first set or the second set can be configured to switch operating between the first modified base frequency or the second modified base frequency.Type: GrantFiled: November 8, 2019Date of Patent: May 16, 2023Assignee: Intel CorporationInventors: Stephen T. Palermo, Nikhil Gupta, Vasudevan Srinivasan, Christopher MacNamara, Sarita Maini, Abhishek Khade, Edwin Verplanke, Lokpraveen Mosur
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Publication number: 20230109635Abstract: Various approaches for the deployment and use of communication exclusion zones, defined for use with a satellite non-terrestrial network (including within a low-earth orbit satellite constellation), are discussed. In an example, defining and implementing a non-terrestrial communication exclusion zone includes: calculating based on a future orbital position of a low-earth orbit satellite vehicle, an exclusion condition for communications from the satellite vehicle; identifying, based on the exclusion condition and the future orbital position, a timing for implementing the exclusion condition for the communications from the satellite vehicle; and generating exclusion zone data for use by the satellite vehicle, the exclusion zone data indicating the timing for implementing the exclusion condition for the communications from the satellite vehicle.Type: ApplicationFiled: March 26, 2021Publication date: April 6, 2023Inventors: Stephen T. Palermo, Chetan Hiremath, Rajesh Gadiyar, Jason K. Smith, Valerie J. Parker, Udayan Mukherjee, Neelam Chandwani, Francesc Guim Bernat, Ned M. Smith
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Publication number: 20230062253Abstract: Various systems and methods for implementing a multi-access edge computing (MEC) based system to realize 5G Network Edge and Core Service Dimensioning using Machine Learning and other Artificial Intelligence Techniques, for improved operations and usage of computing and networking resources, and are disclosed herein. In an example, processing circuitry of a compute node on a network is used to analyze execution of an application to obtain operational data. The compute node then may modularize functions of the application based on the operational data to construct modularized functions. A phase transition graph is constructed using a machine-learning based analysis, the phase transition graph representing state transitions from one modularized function to another modularized function, where the phase transition graph is used to dimension the application by distributing the modularized functions across the network.Type: ApplicationFiled: August 8, 2022Publication date: March 2, 2023Inventors: Mrittika Ganguli, Stephen T. Palermo, Valerie J. Parker
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Patent number: 11537419Abstract: Disclosed is a source host including a processor. The processor operates a virtual machine (VM) to communicate network traffic over a communication link. The processor also initiates migration of the VM to a destination host. The processor also suspends the VM during migration of the VM to the destination host. The source host also includes a live migration circuit coupled to the processor. The live migration circuit manages a session associated with the communication link while the VM is suspended during migration. The live migration circuit buffers changes to a session state and transfers the buffered session state changes to the destination host for replay after the VM is reactivated on the destination host. The live migration circuit keeps the sessions alive during migration to alleviate connection losses.Type: GrantFiled: December 30, 2016Date of Patent: December 27, 2022Assignee: Intel CorporationInventors: Stephen T. Palermo, Krishnamurthy Jambur Sathyanarayana, Sean Harte, Thomas Long, Eliezer Tamir, Hari K. Tadepalli
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Publication number: 20220345210Abstract: Various approaches for the deployment and coordination of inter-satellite communication pathways, defined for use with a satellite non-terrestrial network, are discussed. Among other examples, such inter-satellite communication pathways may be identified, reserved, allocated, and used for ultra-low-latency communication purposes.Type: ApplicationFiled: June 24, 2022Publication date: October 27, 2022Inventors: Stephen T. Palermo, Valerie J. Parker, Udayan Mukherjee, Rajesh Gadiyar, Jason K. Smith
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Patent number: 11431351Abstract: A compression scheme can be selected for an input data stream based on characteristics of the input data stream. For example, when the input data stream is searched for pattern matches, input stream characteristics used to select a compression scheme can include one or more of: type and size of an input stream, a length of a pattern, a distance from a start of where the pattern is to be inserted to the beginning of where the pattern occurred previously, a gap between two pattern matches (including different or same patterns), standard deviation of a length of a pattern, standard deviation of a distance from a start of where the pattern is to be inserted to the beginning of where the pattern occurred previously, or standard deviation of a gap between two pattern matches. Criteria can be established whereby one or more characteristics are used to select a particular encoding scheme.Type: GrantFiled: March 8, 2019Date of Patent: August 30, 2022Assignee: Intel CorporationInventors: David K. Cassetti, Stephen T. Palermo, Sailesh Bissessur, Patrick Fleming, Lokpraveen Mosur, Smita Kumar, Pradnyesh S. Gudadhe, Naveen Lakkakula, Brian Will, Atul Kwatra
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Patent number: 11412033Abstract: Various systems and methods for implementing a multi-access edge computing (MEC) based system to realize 5G Network Edge and Core Service Dimensioning using Machine Learning and other Artificial Intelligence Techniques, for improved operations and usage of computing and networking resources, and are disclosed herein. In an example, processing circuitry of a compute node on a network is used to analyze execution of an application to obtain operational data. The compute node then may modularize functions of the application based on the operational data to construct modularized functions. A phase transition graph is constructed using a machine-learning based analysis, the phase transition graph representing state transitions from one modularized function to another modularized function, where the phase transition graph is used to dimension the application by distributing the modularized functions across the network.Type: GrantFiled: February 25, 2020Date of Patent: August 9, 2022Assignee: Intel CorporationInventors: Mrittika Ganguli, Stephen T. Palermo, Valerie J. Parker
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Publication number: 20220197685Abstract: Technologies for application-specific network acceleration include a computing device including a processor and an accelerator device such as a field-programmable gate array (FPGA). The processor and the accelerator device are coupled via a coherent interconnect and may be included in a multi-chip package. The computing device binds a virtual machine executed by the processor with an application function unit of the accelerator device via the coherent interconnect. The computing device processes network application data with the virtual machine and the application function unit within a coherency domain maintained with the coherent interconnect. Processing the network data may include processing a packet of a network flow by the virtual machine and processing subsequent packets of the network flow by the application function unit. Other embodiments are described and claimed.Type: ApplicationFiled: August 3, 2021Publication date: June 23, 2022Inventors: Stephen T. Palermo, Gerald Rogers, Shih-Wei Roger Chien, Namakkal Venkatesan, Rajesh Gadiyar
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Publication number: 20220141041Abstract: An apparatus operating as a certificate authority (CA) is described. The apparatus can perform operations including receiving, from a plurality of requesting devices, a request to join a group. The request can include identification information for the group and attestation evidence for the plurality of requesting devices. Responsive to receiving the request, the apparatus can provide a group certificate for the group to the plurality of requesting devices.Type: ApplicationFiled: March 27, 2020Publication date: May 5, 2022Inventors: Bhushan Girishkumar Parikh, Hari K. Tadepalli, Stephen T. Palermo, Thomas Joseph O'Dwyer, Abhilasha Bhargav-Spantzel, Ned M. Smith
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Publication number: 20220103614Abstract: Various systems and methods for implementing a multi-access edge computing (MEC) based system to realize 5G Network Edge and Core Service Dimensioning using Machine Learning and other Artificial Intelligence Techniques, for improved operations and usage of computing and networking resources, and are disclosed herein. In an example, processing circuitry of a compute node on a network is used to analyze execution of an application to obtain operational data. The compute node then may modularize functions of the application based on the operational data to construct modularized functions. A phase transition graph is constructed using a machine-learning based analysis, the phase transition graph representing state transitions from one modularized function to another modularized function, where the phase transition graph is used to dimension the application by distributing the modularized functions across the network.Type: ApplicationFiled: February 25, 2020Publication date: March 31, 2022Inventors: Mrittika Ganguli, Stephen T. Palermo, Valerie J. Parker