Abstract: A computer interconnect system uses packet data transmission over serial links connecting nodes of a network. The serial links may provide simultaneous dual paths for transmit/receive. An adapter couples a CPU or the like at a node to the serial link. The adapter includes a packet memory for temporarily storing transmit packets and receive packets, along with a port processor for executing the protocol. Packets of data are transferred between the system bus of the CPU and the packet memory by a pair of data movers, one for read and one for write. All of the serial links of the system are connected to a distribution hub which forwards a transmitted packet to a destination node based upon an address sent with the packet. If the path to the destination node is busy, the hub returns a "flow control" signal to the source node, and in response to this signal the transmitted packet is aborted so that time on the network is not wasted by needless transmission that must be discarded.

Abstract: A digital data processing system including a number of input/output units that communicate with a memory over an input/output bus and through an input/output interface. The input/output interface pipelines data transfers between the input/output units and the memory. The interface includes an incoming and outgoing buffer for queuing requests from the input/output units, and transfers from the memory. In the event of an error in the input/output interface's pipeline buffer, the interface transmits, by means of a fault cycle over the bus, information to the input/output unit that initiated the transfer unit to enable it to recover.