Abstract: A direct digital synthesizer (DDS) includes a phase increment calculator that determines a phase increment for a selected frequency; a phase accumulator that accumulates the phase increment over time and provides an accumulated phase value; a converter that converts the accumulated phase value to an analog signal at the selected frequency; and a phase preset calculator that determines a phase preset value for the selected frequency. The phase accumulator resets the accumulated phase value to the phase preset value at a transition to the selected frequency in a phase coherent mode.

Abstract: In one embodiment, a signal control system has a signal output and includes: 1) a phase-locked loop (PLL) having a voltage-controlled oscillator (VCO), a phase error detector, an oscillating output coupled to the signal output of the signal control system, and a programmable frequency divider coupled in a feedback path between the oscillating output and the phase error detector; 2) at least one automatic level controller (ALC), coupled to the oscillating output; and 3) a plurality of switchable integrators, including first and second switchable integrators that are respectively coupled between the phase error detector and the VCO, and in the at least one ALC. Each of the switchable integrators is switchable between a narrow bandwidth mode that provides for stable operation of the signal control system, and a wide bandwidth mode that enables fast signal transitions at the signal output.

Abstract: In one embodiment, a signal control system has a signal output and includes: 1) a phase-locked loop (PLL) having a voltage-controlled oscillator (VCO), a phase error detector, an oscillating output coupled to the signal output of the signal control system, and a programmable frequency divider coupled in a feedback path between the oscillating output and the phase error detector; 2) at least one automatic level controller (ALC), coupled to the oscillating output; and 3) a plurality of switchable integrators, including first and second switchable integrators that are respectively coupled between the phase error detector and the VCO, and in the at least one ALC. Each of the switchable integrators is switchable between a narrow bandwidth mode that provides for stable operation of the signal control system, and a wide bandwidth mode that enables fast signal transitions at the signal output.

Abstract: Staggered consecutive Nyquist regions associated with differing DAC synthesizer clock rates (FCLK) avoids spectrum lost through disjoint guard bands at the end of or between adjacent Nyquist regions. The staggered consecutive Nyquist regions overlap by an amount at least as much as is consumed by the guard bands. Selectable reconstruction filters associated with each Nyquist region and its DAC clock rate are used to enforce the staggered Nyquist regions and their various guard bands.

Abstract: Staggered consecutive Nyquist regions associated with differing DAC synthesizer clock rates (FCLK) avoids spectrum lost through disjoint guard bands at the end of or between adjacent Nyquist regions. The staggered consecutive Nyquist regions overlap by an amount at least as much as is consumed by the guard bands. Selectable reconstruction filters associated with each Nyquist region and its DAC clock rate are used to enforce the staggered Nyquist regions and their various guard bands. For example, and neglecting guard bands, an initial raw band of operation RB1 may be the First Nyquist region for a basic sampling frequency Fs. An adjacent raw band of operation RB2 that overlaps RB1 may be the Second Nyquist region for an alternate sampling frequency 2Fs/3. An adjacent raw band of operation RB3 that overlaps RB2 may be the Second Nyquist region for the basic sampling frequency Fs. These raw bands overlap: In this example the smallest overlap is Fs/6.

Abstract: Modulated differential (balanced) drive signals are created where, at least one of the signals can be controlled in phase relative to the other, and both of which could be controlled in amplitude and both of which have the same modulation envelope. In one embodiment, a coherent signal is generated in a first electronic signal generator (ESG) and applied to a second ESG. The coherent signal replaces the normal input signal of the second ESG and the I and Q inputs of the second ESG control the amplitude and phase of the output signal. This output signal is applied to a third ESG replacing the normal input signal to the vector modulator.

Abstract: An amplitude control system uses a pair of parallel integrators to rapidly adjust the amplitude of a test signal between two precisely determined power levels in an RF signal generator. The amplitude control system initializes a first power level by switching a first integrator into a feedback signal path to establish a first drive voltage, corresponding to the first power level. A second power level is initialized by switching a second integrator into the feedback signal path to establish a second drive voltage, corresponding to the second power level. The amplitude control system then alternately switches each of the integrators into the feedback signal path to alternately apply the first and second drive voltages to a level modulator, which rapidly adjusts the amplitude of the test signal to each of the two initialized power levels.

Abstract: A remote calibrated power source system comprises an instrument for generating power, the instrument being positioned at a first location, and a remote calibrated power source module for outputting calibrated power, the remote module being positioned at a second location that is removed from the first location. The remote module includes power sampling means for sampling the power generated by the instrument and generating a sampled voltage, the power sampling means having inherent frequency errors, a compensation circuit for generating a frequency-varying correction voltage, and summing amplifier means for receiving both the correction voltage and the sampled voltage and generating a compensated sampled voltage.