Abstract: A scalable solution to managing congestion in a network is disclosed. In one implementation, such a solution comprises a means for managing traffic including at least one flow monitor and a plurality of flow control regulators that together manage congestion within a network. Each of the flow control regulators monitor traffic at a corresponding ingress point and determine a state of the ingress point corresponding to the traffic monitored at the ingress point. Each flow control regulators forward the state (or information representative of the state) to the flow monitor. The flow monitor detects congestion based upon the states of the flow control regulators and, in the event of congestion, determines a target bandwidth for the ingress points. The flow monitor provides a control signal to at least one of the flow control regulators, and at least one of the flow control regulators control flows at its corresponding ingress point based upon the control signal received from the flow monitor.

Abstract: A scalable solution to managing congestion in a network is disclosed. In one implementation, such a solution comprises a means for managing traffic including at least one flow monitor and a plurality of flow control regulators that together manage congestion within a network. Each of the flow control regulators monitor traffic at a corresponding ingress point and determine a state of the ingress point corresponding to the traffic monitored at the ingress point. Each flow control regulators forward the state (or information representative of the state) to the flow monitor. The flow monitor detects congestion based upon the states of the flow control regulators and, in the event of congestion, determines a target bandwidth for the ingress points. The flow monitor provides a control signal to at least one of the flow control regulators, and at least one of the flow control regulators control flows at its corresponding ingress point based upon the control signal received from the flow monitor.

Abstract: A scalable solution to managing fairness in a congested hierarchical switched system is disclosed. The solution comprises a means for managing fairness during congestion in a hierarchical switched system comprising a first level arbitration system and a second level arbitration system of a stage. The first level arbitration system comprises a plurality of arbitration segments that arbitrate between information flows received from at least one ingress point based upon weights associated with those information flows (or the ingress points). Each arbitration segment determines an aggregate weight from each active ingress point providing the information flows to the segment and forwards a selected information flow along with the aggregate weight (in-band or out-of-band) to the second level arbitration system.

Abstract: A method and system for aggregating a plurality of links to simulate a unitary connection among one or more nodes in a fibre channel system includes means for striping data frames across the links. One or more programmable hardware mechanisms, operatively connectable to the links and to nodes in the fabric, also are provided. A program for collecting information about variable link characteristics is included. Programmable hardware mechanisms provide in-order delivery of data frames across the links despite the variable link characteristics.

Abstract: A method and apparatus are presented for operating a time slicing shared memory switch. The apparatus includes a bus for receiving a plurality of data frames in a respective plurality of input channels to the switch. A slice crosspoint applies the plurality of data frames to a shared memory in a time sliced manner. The time slice is established for each section of a shared memory to be staggered so that on any clock cycle, one memory portion is being accessed for writing at least some of the data frames and on a next clock cycle the memory portion is accessed for reading at least a portion of the data.

Abstract: A Fiber Channel circuit (150) has a Fiber Channel switch (152) that receives data frames on input ports (142) and writes the frames to a data storage device (158) from an output port (156) A port server (162) backs up the frames to a data storage backup device (160) by reading data volumes from the data storage device (158) and writing backup copies of at least some of the read data volumes to the data storage backup device (160) A data monitor (166) receives the frame data from the output port and applies it to the data storage device (158) The data monitor (166) also applies it to the port server (162) The port server (162) identifies frames in the volume that have been changed during the backup process. The identified frames are either reread from the data storage array (158), or from a memory (168) associated with the port server (162), and written to the data storage backup device (160).

Abstract: A method and apparatus are presented for operating a time slicing shared memory switch. The apparatus includes a bus for receiving a plurality of data frames in a respective plurality of input channels to the switch. A slice crosspoint applies the plurality of data frames to a shared memory in a time sliced manner. The time slice is established for each section of a shared memory to be staggered so that on any clock cycle, one memory portion is being accessed for writing at least some of the data frames and on a next clock cycle the memory portion is accessed for reading at least a portion of the data.

Abstract: A method and apparatus are presented for operating a time slicing shared memory switch. The apparatus includes a bus for receiving a plurality of data frames in a respective plurality of input channels to the switch. A slice crosspoint applies the plurality of data frames to a shared memory in a time sliced manner. The time slice is established for each section of a shared memory to be staggered so that on any clock cycle, one memory portion is being accessed for writing at least some of the data frames and on a next clock cycle the memory portion is accessed for reading at least a portion of the data.

Abstract: A method and system for aggregating a plurality of links to simulate a unitary connection among one or more nodes in a fibre channel system includes means for striping data frames across the links. One or more programmable hardware mechanisms, operatively connectable to the links and to nodes in the fabric, also are provided. A program for collecting information about variable link characteristics is included. Programmable hardware mechanisms provide in-order delivery of data frames across the links despite the variable link characteristics.

Abstract: A Fiber Channel circuit (150) has a Fiber Channel switch (152) that receives data frames on input ports (142) and writes the frames to a data storage device (158) from an output port (156) A port server (162) backs up the frames to a data storage backup device (160) by reading data volumes from the data storage device (158) and writing backup copies of at least some of the read data volumes to the data storage backup device (160) A data monitor (166) receives the frame data from the output port and applies it to the data storage device (158) The data monitor (166) also applies it to the port server (162) The port server (162) identifies frames in the volume that have been changed during the backup process. The identified frames are either reread from the data storage array (158), or from a memory (168) associated with the port server (162), and written to the data storage backup device (160).

Abstract: A method and apparatus are presented for operating a time slicing shared memory switch. The apparatus includes a bus for receiving a plurality of data frames in a respective plurality of input channels to the switch. A slice crosspoint applies the plurality of data frames to a shared memory in a time sliced manner. The time slice is established for each section of a shared memory to be staggered so that on any clock cycle, one memory portion is being accessed for writing at least some of the data frames and on a next clock cycle the memory portion is accessed for reading at least a portion of the data.

Abstract: A method and apparatus are presented for operating a time slicing shared memory switch. The apparatus includes a bus for receiving a plurality of data frames in a respective plurality of input channels to the switch. A slice crosspoint applies the plurality of data frames to a shared memory in a time sliced manner. The time slice is established for each section of a shared memory to be staggered so that on any clock cycle, one memory portion is being accessed for writing at least some of the data frames and on a next clock cycle the memory portion is accessed for reading at least a portion of the data.