Patents by Inventor Stephen Trinh

Stephen Trinh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190259971
    Abstract: Disclosed herein are organic photosensitive devices including at least one exciton-blocking charge carrier filter. The filters comprise a mixture of at least one wide energy gap material and at least one electron or hole conducting material. As described herein, the novel filters simultaneously block excitons and conduct the desired charge carrier (electrons or holes).
    Type: Application
    Filed: August 31, 2018
    Publication date: August 22, 2019
    Inventors: Stephen R. Forrest, Xin Xiao, Jeramy D. Zimmerman, Kevin Bergemann, Anurag Panda, Brian E. Lassiter, Mark E. Thompson, Andrew N. Bartynski, Cong Trinh
  • Publication number: 20180166130
    Abstract: A method of controlling a memory device can include: receiving, by an interface, a write command from a host; beginning execution of a write operation on a first array plane of a memory array in response to the write command, where the memory array includes a plurality of memory cells arranged in a plurality of array planes; receiving, by the interface, a read command from the host; reconfiguring the write operation in response to detection of the read command during execution of the write operation; beginning execution of a read operation on a second array plane in response to the read command; and restoring the configuration of the write operation after the read operation has at least partially been executed.
    Type: Application
    Filed: May 2, 2016
    Publication date: June 14, 2018
    Applicant: Adesto technologies Corporation
    Inventors: Gideon Intrater, Bard Pedersen, Shane Hollmer, Derric Lewis, Stephen Trinh
  • Patent number: 9812200
    Abstract: A method of controlling an NVM device can include: (i) receiving, by an interface, a write command from a host; (ii) beginning execution of a write operation on a first array plane of a memory array in response to the write command, where the memory array includes a plurality of NVM cells arranged in a plurality of array planes; (iii) receiving, by the interface, a read command from the host; (iv) suspending the write operation in response to detection of the read command during execution of the write operation; (v) beginning execution of a read operation on a second array plane in response to the read command; and (vi) resuming the write operation after the read operation has at least partially been executed.
    Type: Grant
    Filed: May 22, 2015
    Date of Patent: November 7, 2017
    Assignee: Adesto Technologies Corporation
    Inventors: Gideon Intrater, Bard Pedersen, Shane Hollmer, Derric Lewis, Stephen Trinh
  • Patent number: 9483108
    Abstract: A memory device includes a voltage regulator, whose output provides a voltage supply for various other components of the memory device, including a command user interface. The memory device is placed into an ultra-deep power-down mode by providing to the memory device a software command, which causes the output of the voltage regulator to be disabled. To bring the memory device out of the ultra-deep power-down mode, a chip select signal is provided to the memory device, which includes a wake-up circuit that remains powered on even when the memory device is in the ultra-deep power-down mode. Receipt of the chip select signal while the memory device is in the ultra-deep power-down mode causes the output of the voltage regulator to be enabled, thereby providing power to the components that were completely powered down.
    Type: Grant
    Filed: April 28, 2015
    Date of Patent: November 1, 2016
    Assignee: Artemis Acquisition LLC
    Inventors: Richard V. De Caro, Danut Manea, Yongliang Wang, Stephen Trinh, Paul Hill
  • Publication number: 20160012891
    Abstract: A method of controlling an NVM device can include: (i) receiving, by an interface, a write command from a host; (ii) beginning execution of a write operation on a first array plane of a memory array in response to the write command, where the memory array includes a plurality of NVM cells arranged in a plurality of array planes; (iii) receiving, by the interface, a read command from the host; (iv) suspending the write operation in response to detection of the read command during execution of the write operation; (v) beginning execution of a read operation on a second array plane in response to the read command; and (vi) resuming the write operation after the read operation has at least partially been executed.
    Type: Application
    Filed: May 22, 2015
    Publication date: January 14, 2016
    Inventors: Gideon Intrater, Bard Pedersen, Shane Hollmer, Derric Lewis, Stephen Trinh
  • Publication number: 20150241956
    Abstract: A memory device includes a voltage regulator, whose output provides a voltage supply for various other components of the memory device, including a command user interface. The memory device is placed into an ultra-deep power-down mode by providing to the memory device a software command, which causes the output of the voltage regulator to be disabled. To bring the memory device out of the ultra-deep power-down mode, a chip select signal is provided to the memory device, which includes a wake-up circuit that remains powered on even when the memory device is in the ultra-deep power-down mode. Receipt of the chip select signal while the memory device is in the ultra-deep power-down mode causes the output of the voltage regulator to be enabled, thereby providing power to the components that were completely powered down.
    Type: Application
    Filed: April 28, 2015
    Publication date: August 27, 2015
    Inventors: Richard V. De Caro, Danut Manea, Yongliang Wang, Stephen Trinh, Paul Hill
  • Patent number: 9037890
    Abstract: A memory device includes a voltage regulator, whose output provides a voltage supply for various other components of the memory device, including a command user interface. The memory device is placed into an ultra-deep power-down mode by providing to the memory device a software command, which causes the output of the voltage regulator to be disabled. To bring the memory device out of the ultra-deep power-down mode, a chip select signal is provided to the memory device, which includes a wake-up circuit that remains powered on even when the memory device is in the ultra-deep power-down mode. Receipt of the chip select signal while the memory device is in the ultra-deep power-down mode causes the output of the voltage regulator to be enabled, thereby providing power to the components that were completely powered down.
    Type: Grant
    Filed: July 26, 2012
    Date of Patent: May 19, 2015
    Assignee: Artemis Acquisition LLC
    Inventors: Richard V De Caro, Danut Manea, Yongliang Wang, Stephen Trinh, Paul Hill
  • Patent number: 8885413
    Abstract: Systems and techniques for performing write operations on non-volatile memory are described. A described system includes a memory structure including non-volatile memory cells that are arranged on word lines and bit lines and a microcontroller that is communicatively coupled with the memory structure. The memory structure can include non-volatile memory cells that are arranged on word lines and bit lines. The microcontroller can be configured to receive data to write to the memory structure, write the data to the memory structure using a selected word line of the word lines, detect a failure to write the data, apply, based on the failure, a negative bias voltage to one or more unselected word lines of the word lines during a negative bias period, and write the data to the portion of the memory cells using the selected word line during the negative bias period.
    Type: Grant
    Filed: March 20, 2012
    Date of Patent: November 11, 2014
    Assignee: Atmel Corporation
    Inventors: Danut Manea, Erwin Castillon, Uday Mudumba, Sabina Centazzo, Stephen Trinh, Dixie Nguyen
  • Publication number: 20140032956
    Abstract: A memory device includes a voltage regulator, whose output provides a voltage supply for various other components of the memory device, including a command user interface. The memory device is placed into an ultra-deep power-down mode by providing to the memory device a software command, which causes the output of the voltage regulator to be disabled. To bring the memory device out of the ultra-deep power-down mode, a chip select signal is provided to the memory device, which includes a wake-up circuit that remains powered on even when the memory device is in the ultra-deep power-down mode. Receipt of the chip select signal while the memory device is in the ultra-deep power-down mode causes the output of the voltage regulator to be enabled, thereby providing power to the components that were completely powered down.
    Type: Application
    Filed: July 26, 2012
    Publication date: January 30, 2014
    Applicant: Atmel Corporation
    Inventors: Richard V. De Caro, Danut Manea, YONGLIANG WANG, Stephen Trinh, Paul Hill
  • Publication number: 20130250692
    Abstract: Systems and techniques for performing write operations on non-volatile memory are described. A described system includes a memory structure including non-volatile memory cells that are arranged on word lines and bit lines and a microcontroller that is communicatively coupled with the memory structure. The memory structure can include non-volatile memory cells that are arranged on word lines and bit lines. The microcontroller can be configured to receive data to write to the memory structure, write the data to the memory structure using a selected word line of the word lines, detect a failure to write the data, apply, based on the failure, a negative bias voltage to one or more unselected word lines of the word lines during a negative bias period, and write the data to the portion of the memory cells using the selected word line during the negative bias period.
    Type: Application
    Filed: March 20, 2012
    Publication date: September 26, 2013
    Applicant: ATMEL CORPORATION
    Inventors: Danut Manea, Erwin Castillon, Uday Mudumba, Sabina Centazzo, Stephen Trinh, Dixie Nguyen
  • Patent number: 7515469
    Abstract: A column redundancy system for a non-volatile memory includes a separate companion controller chip that includes a column redundancy RAM memory array for storing addresses of defective non-volatile memory cells. Column redundancy match logic provides a match output signal corresponding to a match of a particular user input address for the non-volatile memory with the address of a defective non-volatile memory cell, the collection of said addresses stored in the column redundancy RAM memory array. Column redundancy replacement logic, in response to a match output, dynamically substitutes correct data associated with a defective non-volatile memory cell into an I/O program or read data bit stream of the non-volatile memory chip.
    Type: Grant
    Filed: September 27, 2007
    Date of Patent: April 7, 2009
    Assignee: Atmel Corporation
    Inventors: Alan Chen, Neville Ichhaporia, Vijay P. Adusumilli, Stephen Trinh
  • Publication number: 20090086541
    Abstract: A column redundancy system for a non-volatile memory includes a separate companion controller chip that includes a column redundancy RAM memory array for storing addresses of defective non-volatile memory cells. Column redundancy match logic provides a match output signal corresponding to a match of a particular user input address for the non-volatile memory with the address of a defective non-volatile memory cell, the collection of said addresses stored in the column redundancy RAM memory array. Column redundancy replacement logic, in response to a match output, dynamically substitutes correct data associated with a defective non-volatile memory cell into an I/O program or read data bit stream of the non-volatile memory chip.
    Type: Application
    Filed: September 27, 2007
    Publication date: April 2, 2009
    Applicant: ATMEL CORPORATION
    Inventors: Alan Chen, Neville Ichhaporia, Vijay P. Adusumilli, Stephen Trinh
  • Publication number: 20070097760
    Abstract: A memory system incorporating redundancy utilizes a content addressable memory to monitor addresses during memory accesses. The content addressable memory provides a pointer to an alternate memory location when a previously determined faulty location is requested. Redundant memory cells are accessed by use of column redundancy information output from the content addressable memory. During a memory access cycle a register in the content addressable memory latches a memory address. The content addressable memory decodes the address and produces column redundancy information as an output. The column redundancy information is latched during a period complementary to the memory access cycle. By utilizing complementary memory access phases to latch memory addresses in contrast with a utilization of column redundancy information, a single set of registers may be used. Additionally, concurrent read and write operations are supported.
    Type: Application
    Filed: November 3, 2005
    Publication date: May 3, 2007
    Inventors: Stephen Trinh, Dixie Nguyen
  • Publication number: 20070025160
    Abstract: A post-erase channel clearing procedure for double well, floating gate, non-volatile memory cells. The channel is cleared of charged particles coming from the floating gate after an erase operation in two steps. In the first step the charged particles are pushed into an upper substrate well below the floating gate but not allowed into a deeper well of opposite conductivity type relative to the upper well. After a brief time, T, the charged particles are pushed by a bias voltage into the deeper well from the upper well. This two step clearing procedure avoids device latchup that might occur otherwise.
    Type: Application
    Filed: July 27, 2005
    Publication date: February 1, 2007
    Inventor: Stephen Trinh