Abstract: A software and hardware system and an associated methodology provides ATE-independent go/no-go testing as well as advanced failure diagnosis of integrated circuits for silicon debug, process characterization, production (volume) testing, and system diagnosis comprises an embedded test architecture designed within an integrated circuit; means for seamlessly transferring information between the integrated circuit and its external environment; and an external environment that effectuates the seamless transfer for the user to perform relevant test and diagnosis.

Abstract: A software and hardware system and an associated methodology provides ATE-independent go/no-go testing as well as advanced failure diagnosis of integrated circuits for silicon debug, process characterization, production (volume) testing, and system diagnosis comprises an embedded test architecture designed within an integrated circuit; means for seamlessly transferring information between the integrated circuit and its external environment; and an external environment that effectuates the seamless transfer for the user to perform relevant test and diagnosis.

Abstract: An integrated circuit comprising logic circuits and self-test circuits for testing logic circuits including a pseudo random pattern generator for generating at least one pseudo random pattern and weighing circuit for weighing the pseudo random pattern. The weighting circuit and pseudo random pattern generator generate a plurality of weighted pseudo random patterns including at least one pair of a first weighted pseudo random pattern and a second weighted pseudo random pattern that is the complement of the first pattern. A weighting instruction selects one of the first or second pseudo random patterns for testing the logic circuits.