Abstract: A system comprises a first node that provides a broadcast request for data. The first node receives a read conflict response to the broadcast request from the first node. The read conflict response indicates that a second node has a pending broadcast read request for the data. A third node provides the requested data to the first node in response to the broadcast request from the first node. The first node fills the data provided by the third node in a cache associated with the first node.

Abstract: A system includes a first node that broadcasts a request for data. A second node having a first state associated with the data defines the second node as an ordering point for the data. The second node provides a response to the first node that transfers the ordering point to the first node in response to the request for the data.

Abstract: A computer system supports a first set of processors configured to operate in a dirty-shared mode and a second set of processors configured to operate in a non dirty-shared mode. The computer system may include a portion of shared memory that stores data in terms of memory blocks. Upon receiving a snoop read requesting shared access to a memory block held in a dirty state, a dirty-shared processor sends a copy of the memory block to the originator of the snoop read and retains a valid a copy of the block in its cache. Non dirty-shared processors additionally write the block back to main memory in response to snoop reads and may also send a copy to the originator. Until the write back is completed at main memory or another processor is granted write access to the block, the dirty-shared and non dirty-shared processors preferably continue to satisfy subsequent snoop reads targeting the memory block.

Abstract: Systems and methods are disclosed for interaction between different cache coherency protocols. One system may comprise a home node that receives a request for data from a first node in a first cache coherency protocol. A second node provides a conflict response to a request for the data from the home node. The conflict response indicates that an ordering point for the data is migrating according to a second cache coherency protocol, which is different from the first cache coherency protocol.

Abstract: A system comprises a first node including data having an associated D-state and a second node operative to provide a source broadcast requesting the data. The first node is operative in response to the source broadcast to provide the data to the second node and transition the state associated with the data at the first node from the D-state to an O-state without concurrently updating memory. An S-state is associated with the data at the second node.

Abstract: Systems and methods are disclosed for blocking data responses. One system includes a target node that, in response to a source broadcast request for requested data, provides a response that includes a copy of the requested data. The target node also provides a blocking message to a home node associated with the requested data. The blocking message being operative cause the home node to provide a non-data response to the source broadcast request if the blocking message is matched with the source broadcast request at the home node.

Abstract: A system comprises a first node that employs a source broadcast protocol to initiate a transaction. The first node employs a forward progress protocol to resolve the transaction if the source broadcast protocol cannot provide a deterministic resolution of the transaction.

Abstract: A system comprises a first node operative to provide a source broadcast requesting data. The first node associates an F-state with a copy of the data in response to receiving the copy of the data from memory and receiving non-data responses from other nodes in the system. The non-data responses include an indication that at least a second node includes a shared copy of the data. The F-state enabling the first node to serve as an ordering point in the system capable of responding to requests from other nodes in the system with a shared copy of the data.

Abstract: One disclosed embodiment may comprise a system that includes a home node that provides a transaction reference to a requester in response to a request from the requester. The requester provides an acknowledgement message to the home node in response to the transaction reference, the transaction reference enabling the requester to determine an order of requests at the home node relative to the request from the requester.

Abstract: A system comprises a first node including data having an associated state. The associated state of the data at the first node is a modified state. The system also comprises a second node operative to provide a non-migratory source broadcast request for the data. The first node is operative in response to the non-migratory source broadcast request to provide the data to the second node and to transition the associated state of the data at the first node from the modified state to an owner state without updating memory. The second node is operative to receive the data from the first node and assign a shared state to an associated state of the data at the second node.

Abstract: A system comprises a first node that provides a source broadcast request for data. The first node is operable to respond in a first manner to other source broadcast requests for the data while the source broadcast for the data is pending at the first node. The first node is operable to respond in a second manner to the other source broadcast requests for the data in response to receiving an ownership data response at the first node.

Abstract: A system may comprise a first node that includes an ordering point for data, the first node being operative to employ a write-back transaction associated with writing the data back to memory. The first node broadcasts a write-back message to at least one other node in the system in response to an acknowledgement provided by the memory indicating that the ordering point for the data has migrated from the first node to the memory.

Abstract: Multi-processor systems and methods are disclosed that employ speculative source requests to obtain speculative data fills in response to a cache miss. In one embodiment, a source processor generates a speculative source request and a system source request in response to a cache miss. At least one processor provides a speculative data fill to a source processor in response to the speculative source request. The processor system provides a coherent data fill to the processor in response to the system source request.

Abstract: Multi-processor systems and methods are disclosed. One embodiment may comprise a multi-processor system comprising at least one data fill provided to a source processor in response to a source request by the source processor, and a coherent signal generated by the multi-processor system that provides an indication of which data fill of the at least one data fill is a coherent data fill.

Abstract: A distributed processing system includes a cache coherency mechanism that essentially encodes network routing information into sectored presence bits. The mechanism organizes the sectored presence bits as one or more arbitration masks that system switches decode and use directly to route invalidate messages through one or more higher levels of the system. The lower level or levels of the system use local routing mechanisms, such as local directories, to direct the invalidate messages to the individual processors that are holding the data of interest.

Abstract: Data coherency in a multiprocessor system is improved and data latency minimized through the use of data mapping “fill” requests from any one of the multiprocessor CPUs such that the information requested is acquired through the crossbar switch from the same memory module to which the “victim” data in that CPU's cache must be rewritten. With such an arrangement rewrite latency periods for victim data within the crossbar switch is minimized and the 'ships crossing in the night' problem is avoided.

Abstract: A method and apparatus for preventing system wide data dependent stalls is provided. Requests that reach the top of a probe queue and which target data that is not contained in an attached cache memory, are stalled until the data is filled into the appropriate location in cache memory. Only the associated central processor unit's probe queue is stalled and not the entire system. Accordingly, the present invention allows a system to chain together two or more concurrent operations for the same data block without adversely affecting system performance.

Abstract: A memory system has a plurality of interleaved memory ranks that use SDRAMs requiring a periodic refresh, and an arbiter which controls access to the memory ranks and restricts access to a memory rank being refreshed. The memory ranks are interleaved on a memory module. Counting refresh registers on each memory module are associated with the module's memory ranks. The arbiter has its own counting refresh register. At regular intervals, the arbiter broadcasts a refresh signal along with a refresh address to the modules via a transaction bus. The refresh address provided by the arbiter is latched by the refresh registers which then begin counting at a pre-programmed interval. A refresh to a particular memory rank is triggered when a refresh register associated with the memory rank matches a unique identifier assigned to that rank. The arbiter uses its refresh register to identify the memory rank being refreshed, allowing the arbiter to restrict access to that memory rank.

Abstract: A method for preventing inadvertent invalidation of data elements in a system having a separate probe queue and fill queue for each central processing unit, is provided wherein a central processing unit stores a clean data element, that would otherwise have been discarded, in a victim data buffer when it is evicted from cache. The central processing unit subsequently issues a clean-victim command to the system control logic when the readmiss or read-miss-modify command, targeting the data element that maps to the same location in cache as the clean data element, is issued. The clean-victim command causes the duplicate tag store to indicate that the clean data element is no longer stored in that central processing unit's cache. While the data is stored therein, the central processing unit cannot issue a probe message that targets that data until the victim data buffer has been deallocated.

Abstract: Data coherency in a multiprocessor system is improved and data latency minimized through the use of data mapping "fill" requests from any one of the multiprocessor CPUs such that the information requested is acquired through the crossbar switch from the same memory module to which the "victim" data in that CPUs cache must be rewritten. With such an arrangement rewrite latency periods for victim data within the crossbar switch is minimized and the `ships crossing in the night` problem is avoided.