Patents by Inventor Stephen W. Bailey
Stephen W. Bailey has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240118500Abstract: A system comprises an optical fiber, a manipulator assembly, and a control unit. The manipulator assembly comprises a chassis, an optical fiber cleaning assembly housed within the chassis, and a drive mechanism housed within the chassis. The optical fiber cleaning assembly comprises a cleaning tape, a first spool on which the cleaning tape is wound, and a second spool onto which the cleaning tape is drawn after use. The drive mechanism is configured to advance the cleaning tape from the first spool to the second spool such that a portion of the cleaning tape wipes a face of the optical fiber. The control unit is configured to control the drive mechanism to advance the cleaning tape.Type: ApplicationFiled: December 19, 2023Publication date: April 11, 2024Inventors: Matthew D. Rohr Daniel, Troy K. Adebar, David W. Bailey, Stephen J. Blumenkranz, Edward P. Donlon, Mark E. Froggatt, Christopher M. Major, Randall L. Schlesinger
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Patent number: 11938281Abstract: An apparatus for guiding an elongated flexible instrument comprises a variable-length support assembly. The variable-length support assembly includes a first end, a second end, a plurality of support member pairs, and a plurality of eyelets configured to receive the elongated flexible instrument. Each support member pair comprises a first support member linked to a second support member, and each of the plurality of eyelets is movably coupled to at least one of the plurality of support member pairs along a longitudinal central axis between the first end and the second end. The variable-length support assembly is configured to selectively transition from a compressed configuration to an expanded configuration along the longitudinal central axis, and the plurality of eyelets are adapted to support the elongated flexible instrument as the elongated flexible instrument is advanced along the longitudinal central axis.Type: GrantFiled: May 26, 2021Date of Patent: March 26, 2024Assignee: INTUITIVE SURGICAL OPERATIONS, INC.Inventors: Matthew D. Inouye, David W. Bailey, Stephen J. Blumenkranz, Matthew D. Rohr Daniel
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Publication number: 20240095510Abstract: Disclosed is a neuromorphic integrated circuit including, in some embodiments, a multi-layered neural network disposed in an analog multiplier array of two-quadrant multipliers. Each multiplier of the multipliers is wired to ground and draws a negligible amount of current when input signal values for input signals to transistors of the multiplier are approximately zero, weight values of the transistors of the multiplier are approximately zero, or a combination thereof Also disclosed is a method of the neuromorphic integrated circuit including, in some embodiments, training the neural network; tracking rates of change for the weight values; determining if and how quickly certain weight values are trending toward zero; and driving those weight values toward zero, thereby encouraging sparsity in the neural network. Sparsity in the neural network combined with the multipliers wired to ground minimizes power consumption of the neuromorphic integrated circuit such that battery power is sufficient for power.Type: ApplicationFiled: November 28, 2023Publication date: March 21, 2024Inventors: Kurt F. Busch, Jeremiah H. Holleman, III, Pieter Vorenkamp, Stephen W. Bailey
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Publication number: 20240062056Abstract: Provided herein is an integrated circuit including, in some embodiments, a special-purpose host processor, a neuromorphic co-processor, and a communications interface between the host processor and the co-processor configured to transmit information therebetween. The special-purpose host processor can be operable as a stand-alone processor. The neuromorphic co-processor may include an artificial neural network. The co-processor is configured to enhance special-purpose processing of the host processor through an artificial neural network. In such embodiments, the host processor is a pattern identifier processor configured to transmit one or more detected patterns to the co-processor over a communications interface. The co-processor is configured to transmit the recognized patterns to the host processor.Type: ApplicationFiled: October 30, 2023Publication date: February 22, 2024Inventors: Kurt F. Busch, Pieter Vorenkamp, Stephen W. Bailey, Jeremiah H. Holleman, III
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Patent number: 11880226Abstract: A method comprising the steps of responding to expiration of a timer, transmitting a signal from the timer to circuitry; responsive to receiving the signal, retrieving by the circuitry (i) first values stored in an analog array, and (ii) second values stored in a digital non-volatile memory; performing, by the circuitry, operations comprising a comparison of the first values and the second values; analyzing, by the circuitry, results of the comparison to determine whether an error is greater than or equal to a predefined threshold; responsive to determining the error is greater than or equal to the predefined threshold, initiating, by the circuitry, operations to reprogram the analog array with the second value is described.Type: GrantFiled: April 9, 2022Date of Patent: January 23, 2024Assignee: SyntiantInventors: Kurt F. Busch, Jeremiah H. Holleman, III, Pieter Vorenkamp, Stephen W. Bailey
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Patent number: 11868876Abstract: Disclosed is a neuromorphic integrated circuit including, in some embodiments, a multi-layered neural network disposed in an analog multiplier array of two-quadrant multipliers. Each multiplier of the multipliers is wired to ground and draws a negligible amount of current when input signal values for input signals to transistors of the multiplier are approximately zero, weight values of the transistors of the multiplier are approximately zero, or a combination thereof. Also disclosed is a method of the neuromorphic integrated circuit including, in some embodiments, training the neural network; tracking rates of change for the weight values; determining if and how quickly certain weight values are trending toward zero; and driving those weight values toward zero, thereby encouraging sparsity in the neural network. Sparsity in the neural network combined with the multipliers wired to ground minimizes power consumption of the neuromorphic integrated circuit such that battery power is sufficient for power.Type: GrantFiled: January 21, 2022Date of Patent: January 9, 2024Assignee: SyntiantInventors: Kurt F. Busch, Jeremiah H. Holleman, III, Pieter Vorenkamp, Stephen W. Bailey
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Patent number: 11803741Abstract: Provided herein is an integrated circuit including, in some embodiments, a special-purpose host processor, a neuromorphic co-processor, and a communications interface between the host processor and the co-processor configured to transmit information therebetween. The special-purpose host processor can be operable as a stand-alone processor. The neuromorphic co-processor may include an artificial neural network. The co-processor is configured to enhance special-purpose processing of the host processor through an artificial neural network. In such embodiments, the host processor is a pattern identifier processor configured to transmit one or more detected patterns to the co-processor over a communications interface. The co-processor is configured to transmit the recognized patterns to the host processor.Type: GrantFiled: February 13, 2019Date of Patent: October 31, 2023Assignee: SYNTIANTInventors: Kurt F. Busch, Pieter Vorenkamp, Stephen W. Bailey, Jeremiah H. Holleman, III
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Patent number: 11748607Abstract: Provided herein is an integrated circuit including, in some embodiments, a hybrid neural network including a plurality of analog layers, a digital layer, and a plurality of data outputs. The plurality of analog layers is configured to include programmed weights of the neural network for decision making by the neural network. The digital layer, disposed between the plurality of analog layers and the plurality of data outputs, is configured for programming to compensate for weight drifts in the programmed weights of the neural network, thereby maintaining integrity of the decision making by the neural network. Also provided herein is a method including, in some embodiments, programming the weights of the plurality of analog layers; determining the integrity of the decision making by the neural network; and programming the digital layer of the neural network to compensate for the weight drifts in the programmed weights of the neural network.Type: GrantFiled: July 27, 2018Date of Patent: September 5, 2023Assignee: SyntiantInventors: Kurt F. Busch, Jeremiah H. Holleman, III, Pieter Vorenkamp, Stephen W. Bailey
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Publication number: 20220414439Abstract: Disclosed herein is a method for automatically generating an integrated circuit. The method includes receiving a behavioral description of at least the first layer of the neural network, converting the behavioral description of the first layer of the neural network into the computational graph, converting a computational graph to a circuit netlist based on a correlation of: (i) operations described in the computational graph, and (ii) an analog cell library including a plurality of predetermined circuit blocks that describe known neural network operations, generating a circuit layout that corresponds to at least a first layer of a neural network, and performing additional actions configured to cause generation of the integrated circuit based on the circuit layout. In some situations, the behavioral description defines an architecture of machine learning logic that represents at least a portion of the neural network.Type: ApplicationFiled: August 22, 2022Publication date: December 29, 2022Inventors: Pieter Vorenkamp, Kurt F. Busch, Stephen W. Bailey, Jeremiah H. Holleman, III
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Publication number: 20220327384Abstract: Provided herein is a system including, in some embodiments, one or more servers and one or more database servers configured to receive user-specific target information from a client application for training a neural network on a neuromorphic integrated circuit. The one or more database servers are configured to merge the user-specific target information with existing target information to form merged target information in the one or more databases. The system further includes a training set builder and a trainer. The training set builder is configured to build a training set for training a software-based version of the neural network from the merged target information. The trainer is configured to train the software-based version of the neural network with the training set to determine a set of synaptic weights for the neural network on the neuromorphic integrated circuit.Type: ApplicationFiled: June 27, 2022Publication date: October 13, 2022Inventors: Kurt F. Busch, Pieter Vorenkamp, Stephen W. Bailey
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Patent number: 11423288Abstract: Disclosed herein is a method for automatically generating an integrated circuit. The method includes receiving a behavioral description of at least the first layer of the neural network, converting the behavioral description of the first layer of the neural network into the computational graph, converting a computational graph to a circuit netlist based on a correlation of: (i) operations described in the computational graph, and (ii) an analog cell library including a plurality of predetermined circuit blocks that describe known neural network operations, generating a circuit layout that corresponds to at least a first layer of a neural network, and performing additional actions configured to cause generation of the integrated circuit based on the circuit layout. In some situations, the behavioral description defines an architecture of machine learning logic that represents at least a portion of the neural network.Type: GrantFiled: July 18, 2018Date of Patent: August 23, 2022Assignee: SyntiantInventors: Pieter Vorenkamp, Kurt F. Busch, Stephen W. Bailey, Jeremiah H. Holleman, III
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Publication number: 20220237068Abstract: A method comprising the steps of responding to expiration of a timer, transmitting a signal from the timer to circuitry; responsive to receiving the signal, retrieving by the circuitry (i) first values stored in an analog array, and (ii) second values stored in a digital non-volatile memory; performing, by the circuitry, operations comprising a comparison of the first values and the second values; analyzing, by the circuitry, results of the comparison to determine whether an error is greater than or equal to a predefined threshold; responsive to determining the error is greater than or equal to the predefined threshold, initiating, by the circuitry, operations to reprogram the analog array with the second value is described.Type: ApplicationFiled: April 9, 2022Publication date: July 28, 2022Inventors: Kurt F. Busch, Jeremiah H. Holleman, III, Pieter Vorenkamp, Stephen W. Bailey
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Patent number: 11373091Abstract: Provided herein is a system including, in some embodiments, one or more servers and one or more database servers configured to receive user-specific target information from a client application for training a neural network on a neuromorphic integrated circuit. The one or more database servers are configured to merge the user-specific target information with existing target information to form merged target information in the one or more databases. The system further includes a training set builder and a trainer. The training set builder is configured to build a training set for training a software-based version of the neural network from the merged target information. The trainer is configured to train the software-based version of the neural network with the training set to determine a set of synaptic weights for the neural network on the neuromorphic integrated circuit.Type: GrantFiled: October 18, 2018Date of Patent: June 28, 2022Assignee: SyntiantInventors: Kurt F. Busch, Pieter Vorenkamp, Stephen W. Bailey
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Publication number: 20220188619Abstract: Disclosed is a neuromorphic-processing systems including, in some embodiments, a special-purpose host processor operable as a stand-alone host processor; a neuromorphic co-processor including an artificial neural network; and a communications interface between the host processor and the co-processor configured to transmit information therebetween. The co-processor is configured to enhance special-purpose processing of the host processor with the artificial neural network. Also disclosed is a method of a neuromorphic-processing system having the special-purpose host processor and the neuromorphic co-processor including, in some embodiments, enhancing the special-purpose processing of the host processor with the artificial neural network of the co-processor. In some embodiments, the host processor is a hearing-aid processor.Type: ApplicationFiled: February 28, 2022Publication date: June 16, 2022Inventors: Kurt F. Busch, Jeremiah H. Holleman, III, Pieter Vorenkamp, Stephen W. Bailey
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Publication number: 20220157384Abstract: Disclosed herein is a neuromorphic integrated circuit, including in many embodiments, a neural network disposed in a multiplier array in a memory sector of the integrated circuit, and a plurality of multipliers of the multiplier array, a multiplier thereof including at least one transistor-based cell configured to store a synaptic weight of the neural network, an input configured to accept digital input pulses for the multiplier, an output configured to provide digital output pulses of the multiplier, and a charge integrator, where the charge integrator is configured to integrate a current associated with an input pulse of the input pulses over an input pulse width thereof, and where the multiplier is configured to provide an output pulse of the output pulses with an output pulse width proportional to the input pulse width.Type: ApplicationFiled: December 31, 2021Publication date: May 19, 2022Inventors: Kurt F. Busch, Jeremiah H. Holleman, III, Pieter Vorenkamp, Stephen W. Bailey
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Patent number: 11334412Abstract: A method comprising the steps of responding to expiration of a timer, transmitting a signal from the timer to circuitry; responsive to receiving the signal, retrieving by the circuitry (i) first values stored in an analog array, and (ii) second values stored in a digital non-volatile memory; performing, by the circuitry, operations comprising a comparison of the first values and the second values; analyzing, by the circuitry, results of the comparison to determine whether an error is greater than or equal to a predefined threshold; responsive to determining the error is greater than or equal to the predefined threshold, initiating, by the circuitry, operations to reprogram the analog array with the second value is described.Type: GrantFiled: March 15, 2021Date of Patent: May 17, 2022Assignee: SyntiantInventors: Kurt F. Busch, Jeremiah H. Holleman, III, Pieter Vorenkamp, Stephen W. Bailey
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Publication number: 20220147807Abstract: Disclosed is a neuromorphic integrated circuit including, in some embodiments, a multi-layered neural network disposed in an analog multiplier array of two-quadrant multipliers. Each multiplier of the multipliers is wired to ground and draws a negligible amount of current when input signal values for input signals to transistors of the multiplier are approximately zero, weight values of the transistors of the multiplier are approximately zero, or a combination thereof. Also disclosed is a method of the neuromorphic integrated circuit including, in some embodiments, training the neural network; tracking rates of change for the weight values; determining if and how quickly certain weight values are trending toward zero; and driving those weight values toward zero, thereby encouraging sparsity in the neural network. Sparsity in the neural network combined with the multipliers wired to ground minimizes power consumption of the neuromorphic integrated circuit such that battery power is sufficient for power.Type: ApplicationFiled: January 21, 2022Publication date: May 12, 2022Inventors: Kurt F. Busch, Jeremiah H. Holleman, III, Pieter Vorenkamp, Stephen W. Bailey
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Publication number: 20220093085Abstract: Provided herein is an integrated circuit including, in some embodiments, a special-purpose host processor, a neuromorphic co-processor, and a communications interface between the host processor and the co-processor configured to transmit information therebetween. The special-purpose host processor is operable as a stand-alone host processor. The neuromorphic co-processor includes an artificial neural network. The co-processor is configured to enhance special-purpose processing of the host processor through the artificial neural network. In such embodiments, the host processor is a keyword identifier processor configured to transmit one or more detected words to the co-processor over the communications interface. The co-processor is configured to transmit recognized words, or other sounds, to the host processor.Type: ApplicationFiled: December 6, 2021Publication date: March 24, 2022Inventors: Kurt F. Busch, Jeremiah H. Holleman, III, Pieter Vorenkamp, Stephen W. Bailey
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Patent number: 11270198Abstract: Disclosed is a neuromorphic-processing systems including, in some embodiments, a special-purpose host processor operable as a stand-alone host processor; a neuromorphic co-processor including an artificial neural network; and a communications interface between the host processor and the co-processor configured to transmit information therebetween. The co-processor is configured to enhance special-purpose processing of the host processor with the artificial neural network. Also disclosed is a method of a neuromorphic-processing system having the special-purpose host processor and the neuromorphic co-processor including, in some embodiments, enhancing the special-purpose processing of the host processor with the artificial neural network of the co-processor. In some embodiments, the host processor is a hearing-aid processor.Type: GrantFiled: July 28, 2018Date of Patent: March 8, 2022Assignee: SyntiantInventors: Kurt F. Busch, Jeremiah H. Holleman, III, Pieter Vorenkamp, Stephen W. Bailey
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Patent number: 11232349Abstract: Disclosed is a neuromorphic integrated circuit including, in some embodiments, a multi-layered neural network disposed in an analog multiplier array of two-quadrant multipliers. Each multiplier of the multipliers is wired to ground and draws a negligible amount of current when input signal values for input signals to transistors of the multiplier are approximately zero, weight values of the transistors of the multiplier are approximately zero, or a combination thereof. Also disclosed is a method of the neuromorphic integrated circuit including, in some embodiments, training the neural network; tracking rates of change for the weight values; determining if and how quickly certain weight values are trending toward zero; and driving those weight values toward zero, thereby encouraging sparsity in the neural network. Sparsity in the neural network combined with the multipliers wired to ground minimizes power consumption of the neuromorphic integrated circuit such that battery power is sufficient for power.Type: GrantFiled: July 20, 2018Date of Patent: January 25, 2022Assignee: SyntiantInventors: Kurt F. Busch, Jeremiah H. Holleman, III, Pieter Vorenkamp, Stephen W. Bailey