Abstract: A fully integrated circuit configuration that can be utilized to prevent abnormal discharge or overcharge in ultra-portable electronic systems is described. This battery protection integrated circuit can be enhanced by the addition of traditional battery protection schemes such as current limiting, overcurrent clamping, under voltage lock out and over voltage protection. This battery protection scheme utilizes a high side switch approach utilizing an ultra-low leakage PMOS power switch rather than the traditional low side NMOS switching.

Abstract: Described are apparatus and methods for control of multi-channel load switches with synchronized power up/down timing sequences. The slew rate control methods of the PMOS load switches contained in the N Multi-channel configuration is also described. A preferred slew rate control circuit includes a power PMOS transistor that is capable of handling load currents of several amperes along with an integrated controller. The integrated controller allows the user to program the power on/off sequences of each of the load switch channels by simply using a single or multiple input enable input pins.

Abstract: A fully integrated circuit configuration that can be used to control the power path of a number of PMOS load switches is described. The circuit has a unique feature that it can automatically select the input voltage to be presented to the VOUT pin based upon the voltage levels at the respective VIN pins. By using combinations of the EN input pin and the SEL input pin, the circuit can be configured to perform one of four functional behaviors: 1. Complete shutdown (both switches in the OFF position), 2. Automatic input selection according the voltage levels that are presented on the VIN pins, 3. Selection of the VIN1 input only, or 4. Selection of the VIN2 input only. This concept is extended to multiple input sources in further embodiments.

Abstract: Described are apparatus and methods for a load switch with reset and deep sleep capability. The slew rate control methods of the PMOS load switches contained in the load switch configuration is also described. A preferred slew rate control circuit includes a power PMOS transistor that is capable of handling load currents of several amperes along with an integrated controller. The integrated reset and deep sleep functions allow the user to control the basic timing control of the voltages that are required by the system and to save battery power in an extended deep sleep mode such as storage and shipping.

Abstract: A fully integrated circuit configuration that can be used to control the power path of a pair of PMOS load switches is described. The circuit also integrates a programmable slew rate for the second PMOS load switch in order to control the power path from the input system voltage (battery or power supply) or from a backup source of power. The integrated circuit configuration also contains a charge pump circuit which can be used to charge the backup source of power to a voltage that is greater than the input voltage.

Abstract: A fully integrated circuit configuration that can be used to control the slew rate of a PMOS load switch is described. The circuit also integrates a multichannel temperature sensing system which can be coupled to an external set of temperature sensors, preferably non-linear PTC (positive temperature coefficient) sensors to provide both current inrush control as well as thermal overload protection. A communications data bus, such as an I2C bus, is employed to provide temperature feedback for the system controller so that the system can better control the temperature of its own environment.

Abstract: A fully integrated circuit configuration that can be used to control the gate voltage of a power NMOS load switch using a unique method of controlling the charge pump voltage by utilizing a feedback loop to regulate the gate voltage and turning off the charge pump periodically in order to save power. This configuration is suitable for load switch applications where the input voltage can be as low as 0.8V.

Abstract: A hysteretic DC-DC converter includes a reference circuit, a hysteretic comparator, and a control circuit. The hysteretic comparator may be configured to compare a monitored output of the converter to a reference signal generated by the reference circuit and to compare a load ground of the output of the converter to a reference signal ground of the reference signal. The hysteretic comparator may perform the aforementioned comparisons simultaneously. The hysteretic comparator may generate a comparator output based on the comparison of the output of the converter to the reference signal and the comparison of the load ground to the reference signal ground. The control circuit may vary a control output to increase or decrease the output of the converter based on the comparator output.

Abstract: A high voltage circuit driver includes high and low side driver cells to drive a high and a low side power MOSFET, a bootstrap circuit to energize the high side driver cell, a high voltage PMOS transistor (HVPMOS) between a voltage source and the bootstrap circuit, wherein the HVPMOS is embedded in an N-isolation layer and is integrated with the driver cells. A bootstrap control circuit, for controlling the HVPMOS, includes a high voltage level shift stage, which can also be embedded in an N-isolation layer. The circuit driver is operated by switching the high side drive signal from high to low, the low side drive signal from low to high with a first delay, and a bootstrap control signal from high to low with an additional second delay. Also, the bootstrap capacitor is first charged by switching on the HVPMOS, and then it energizes the high side driver cell.

Abstract: A high voltage circuit driver includes high and low side driver cells to drive a high and a low side power MOSFET, a bootstrap circuit to energize the high side driver cell, a high voltage PMOS transistor (HVPMOS) between a voltage source and the bootstrap circuit, wherein the HVPMOS is embedded in an N-isolation layer and is integrated with the driver cells. A bootstrap control circuit, for controlling the HVPMOS, includes a high voltage level shift stage, which can also be embedded in an N-isolation layer. The circuit driver is operated by switching the high side drive signal from high to low, the low side drive signal from low to high with a first delay, and a bootstrap control signal from high to low with an additional second delay. Also, the bootstrap capacitor is first charged by switching on the HVPMOS, and then it energizes the high side driver cell.

Abstract: An monolithic programmable dc--dc converter controller integrated circuit with a high speed synchronous controller and a 4-bit programmable DAC to provide an operating voltage to an external device such as a microprocessor in response to a code programmed in the external device. The 4-bit programmable DAC outputs a signal which is combined with a precise reference voltage to provide voltages to the external device in increments of 100 millivolts.

Abstract: A programmable DC-DC converter controller with a high speed synchronous controller and a 5-bit programmable DAC provides an operating voltage to an external device (such as a microprocessor) in response to a 5 bit code programmed in the external device. The 5-bit programmable DAC outputs a signal which provides voltages to the external device in increments of e.g. 50 or 100 millivolts, in respectively two different voltage ranges.

Abstract: A dual adjustable voltage regulator combining a DC--DC switching regulator with a linear regulator implemented on a single chip is disclosed. The invention provides switching circuitry that can select between a fixed output voltage level and a user-adjustable output voltage. The circuit further provides means to automatically detect and generate power supply voltage levels as required by the system.

Abstract: A method and apparatus for adjusting charging and discharging currents of a pin driver to optimize slew rates and overshoot for different types of logic circuits. The current charging and discharging circuits include respective transistors that are mirrored to a transistor whose current varies in accordance with VH-VL where VH and VL are programmed reference voltages defining the high and low voltage levels of the output driver pulses. Thus, when VH-VL is relatively large such as for CMOS outputs, slew rates are relatively high. However, when VH-VL is relatively small such as for ECL outputs, slew rates are reduced to prevent excessive overshoot.

Abstract: A test equipment pin driver having a main output channel including a pulse forming circuit, a buffer and an output amplifier connected in series. The pulse forming circuit provides pulses that are timed to a data input signal, and the buffer passes the pulses to the amplifier which produces driver pulses adapted to be transmitted to a device under test. The high and low voltage levels of the driver pulses are made substantially the same as programmed high and low voltages by providing scaled replicas of the buffer and amplifier, and using closed loop compensation to accurately drive the replica outputs to the high and low programmed voltages, respectively. The replicas mirror the DC performance of the buffer and amplifier of the main output channel, and clamping voltages are provided from the closed loops to enable operation of the main output channel in a manner that produces driver pulses with the programmed high and low voltage levels.

Abstract: A pin driver amplifier having a complementary pair of transistors with a pair of resistors coupled between the respective emitters. A node between the resistors is coupled through an output series resistor to an output terminal adapted for connection of a transmission line that conducts driver pulses of predetermined voltage levels and timing to a device under test. A capacitor is tied between the emitters to provide a substantially constant reverse termination impedance for the transmission line thereby reducing reflections. Also, an RC network is coupled between the output terminal and ground to further reduce reflections. The amplifier transistors are driven by respective buffer transistor emitters that are tied together by a capacitor to make the positive and negative going drive capabilities for the amplifier transistors more equal. Further, capacitors are coupled between the amplifier collectors and ground to provide a bypass for parasitic inductance in the supply voltage wires.