Patents by Inventor Stephen W. Byatt

Stephen W. Byatt has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5955750
    Abstract: A four-region (PNPN) semiconductor device structure that provides greater flexibility in the setting of PN junction breakdown conditions. The four-region (PNPN) semiconductor device includes an additional N-type body at the junction between the inner N-type region and the inner P-type region, the additional N-type body including a first part adjacent to a second part, the first and second parts having different impurity concentrations from one another, both being of high impurity concentration than the inner N-type region and of lower impurity concentration than the inner P-type region.
    Type: Grant
    Filed: August 30, 1995
    Date of Patent: September 21, 1999
    Assignee: Texas Instruments Incorporated
    Inventor: Stephen W. Byatt
  • Patent number: 5429953
    Abstract: This invention relates to an improved solid state suppressor and a method for making the same. Due to the fact that at least part of the substrate is substituted during fabrication of the suppressor, it is possible to produce a suppressor having a substrate which has an effective thickness that is less than the physical thickness of the slice. This allows for a good functioning suppressor which is unlikely to break during fabrication.
    Type: Grant
    Filed: June 11, 1993
    Date of Patent: July 4, 1995
    Assignee: Texas Instruments Incorporated
    Inventor: Stephen W. Byatt
  • Patent number: 5418834
    Abstract: This invention describes a maintenance termination unit often used in telephone lines and particularly the triggering circuit for use in such units. The triggering circuit uses two complementary transistors Q1, Q2 and a diode Z1 along with a resistor R and capacitor C2 in specific electrical connection sequence to provide for "turn-on" by either reaching the preset "turn on" voltage or by having a significantly high rate of voltage rise.
    Type: Grant
    Filed: September 10, 1993
    Date of Patent: May 23, 1995
    Inventors: Stephen W. Byatt, Michael J. Maytum
  • Patent number: 5401984
    Abstract: A semiconductor component for limiting transient voltages on the signal or other supply lines of a system, includes, in a common semiconductor body, a plurality of multi-junction diodes connected in the same sense between a common terminal and respective input means which are for connection to the respective supply lines of the system, and a respective further diode connected in shunt with each multi-junction diode with the opposite sense to the multi-junction diode.
    Type: Grant
    Filed: December 10, 1993
    Date of Patent: March 28, 1995
    Assignee: Texas Instruments Incorporated
    Inventors: Stephen W. Byatt, Michael J. Maytum
  • Patent number: 5359210
    Abstract: An integrated circuit including a first device having respective input and output electrodes at opposed first and second faces of a semiconductor block in which the device is formed, and a second device, formed in the semiconductor block, having its respective input and output electrodes at the first and second faces of the semiconductor block, the electrodes at the first face of the semiconductor block intermingling with each other. In one form of the integrated circuit, the electrode of the first device at the first face of the semiconductor block includes a plurality of discrete contact areas distributed over substantially all of the first face, and the electrode of the second device at the first face includes a contact area which lies between the discrete contact areas.
    Type: Grant
    Filed: October 27, 1992
    Date of Patent: October 25, 1994
    Assignee: Texas Instruments Incorporated
    Inventor: Stephen W. Byatt
  • Patent number: 5317172
    Abstract: A PNPN semiconductor device has an inner P-type region which includes at least one ridge which extends into its outer N-type region and terminates short of the outer boundary of the outer N-type region, the inner P-type region includes a formation which is substantially level with the outer boundary of the outer N-type region, and the device includes a terminal which contacts the outer N-type region and the formation of the inner P-type region.An alternative structure of the PNPN semiconductor device has an inner P-type region having at least one elongate sub-region, of higher conductivity than the remainder of the inner P-type region, lying along the junction between the inner P-type region and the outer N-type region, the formation which is substantially level with the outer boundary of the outer N-type region, and the terminal which contacts the formation and the outer N-type region.
    Type: Grant
    Filed: June 11, 1992
    Date of Patent: May 31, 1994
    Assignee: Texas Instruments Incorporated
    Inventor: Stephen W. Byatt
  • Patent number: 5304823
    Abstract: A semiconductor integrated circuit is provided which can have a high holding current without the penalty of a high gate current. Such a circuit includes a PNPN device and junction bipolar transistor in which a further doped region of the same conductivity type as the transistor collector region and more heavily doped than the collector region prevents the devices affecting each other. The junction bipolar transistor has a current gain of at least 10 and base-collector and base-emitter junctions with reverse breakdown voltages of at least 50 volts. A PN diode can also be used in the circuit.
    Type: Grant
    Filed: September 8, 1992
    Date of Patent: April 19, 1994
    Assignee: Texas Instruments Incorporated
    Inventor: Stephen W. Byatt
  • Patent number: 4629944
    Abstract: A starter circuit for a fluorescent tube lamp is connected between the cathode heaters of the tube to provide an initial heating current and then changes to a high impedance to ignite the tube. The circuit is fed by raw rectified a.c. and has a main thyristor requiring a high holding current to maintain the initial conduction. The current through the main thyristor sets up a voltage across a series diode which triggers a second thyristor to reduce the gate voltage of the main thyristor. The main thyristor ceases conduction when the current falls below the holding value and the inductive ballast impedance then produces a high energy striking pulse for the tube. The pulse voltage is limited to increase its duration. One embodiment generates a single pulse only each time the circuit is switched on and another embodiment produces pulses for a period of time before becoming quiescent. The main thyristor and the voltage limiting means are embodied in a monolithic semiconductor structure.
    Type: Grant
    Filed: February 29, 1984
    Date of Patent: December 16, 1986
    Assignee: Texas Instruments Incorporated
    Inventors: Michael J. Maytum, Anthony Lear, Stephen W. Byatt, Richard A. A. Rodrigues
  • Patent number: 4375125
    Abstract: The surface termination of a p-n junction of a semiconductor device is passivated with semi-insulating material which is deposited on a thin layer of insulating material formed at the bared semiconductor surface by a chemical conversion treatment at a temperature above room temperature. The layer may be formed by oxidizing the semiconductor material of the body for example in dry oxygen between 300.degree. C. and 500.degree. C. or in an oxidizing liquid containing for example hydrogen peroxide or nitric acid at for example 80.degree. C. The layer is sufficiently thin to permit conduction (e.g. by tunnelling) between the semi-insulating material and the surface but thick enough to reduce said conduction so that when the junction is reverse-biased leakage current flows further along the semi-insulating material before flowing out to the surface across the layer.
    Type: Grant
    Filed: March 6, 1981
    Date of Patent: March 1, 1983
    Assignee: U.S. Philips Corporation
    Inventor: Stephen W. Byatt