Abstract: A planar inductor may include a first coil and a second coil. The first coil may include a first trace that forms a first set of turns. The second coil may include a second trace that forms a second set of turns. A distance between the turns of the first set of turns may be equal to a distance between the turns of the second set of turns. A width of the first trace may be equal to a width of the second trace. The first coil and the second coil may be physically positioned or sized according to a/b in which a represents the width of the first trace and b represents the distance between the turns of the first set of turns.

Abstract: A network interface adapted for high speed networks. The interface includes isolation circuits with a transformer containing two primary coils and two secondary coils. A wire making up each primary coil may be twisted with a wire making up a secondary. These two coils may then be co-wound on a common core. The transformer may be connected to a common mode choke. The isolation circuit may be packaged such that the transformer and coil are in a line, with isolation circuits for a plurality of pairs arranged in parallel. The interface circuit may be packaged in a connector housing, which also may be adapted for high speed performance. The housing may receive multiple isolation circuits in parallel. The housing may also include a mating contact portion in which mating contacts for signal conductors of each pair are positioned along the same side of a cavity.

Abstract: A network interface adapted for high speed networks. The interface includes isolation circuits with a transformer containing two primary coils and two secondary coils. A wire making up each primary coil may be twisted with a wire making up a secondary. These two coils may then be co-wound on a common core. The transformer may be connected to a common mode choke. The isolation circuit may be packaged such that the transformer and coil are in a line, with isolation circuits for a plurality of pairs arranged in parallel. The interface circuit may be packaged in a connector housing, which also may be adapted for high speed performance. The housing may receive multiple isolation circuits in parallel. The housing may also include a mating contact portion in which mating contacts for signal conductors of each pair are positioned along the same side of a cavity.