Patents by Inventor Stephen W. Gray

Stephen W. Gray has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11985239
    Abstract: Transport Layer Security (TLS) connection establishment between a client and a server for a new session is enabled using an ephemeral (temporary) key pair. In response to a request, the server generates a temporary certificate by signing an ephemeral public key using the server's private key. A certificate chain comprising at least the temporary certificate that includes the ephemeral public key, together with a server certificate, is output to the client by the server, which acts as a subordinate Certificate Authority. The client validates the certificates, generates a session key and outputs the session key wrapped by the ephemeral public key. To complete the connection establishment, the server applies the ephemeral private key to recover the session key derived at the client for the new session. The client and server thereafter use the session key to encrypt and decrypt data over the link. The ephemeral key pair is not reused.
    Type: Grant
    Filed: October 15, 2021
    Date of Patent: May 14, 2024
    Assignee: International Business Machines Corporation
    Inventors: Michael W. Gray, Narayana Aditya Madineni, Matthew Green, Simon D. McMahon, Leigh S. McLean, Stephen J. McKenzie, Luvita Burgess, Peter T. Waltenberg
  • Patent number: 11977766
    Abstract: A hierarchical network enables access for a stacked memory system including or more memory dies that each include multiple memory tiles. The processor die includes multiple processing tiles that are stacked with the one or more memory die. The memory tiles that are vertically aligned with a processing tile are directly coupled to the processing tile and comprise the local memory block for the processing tile. The hierarchical network provides access paths for each processing tile to access the processing tile's local memory block, the local memory block coupled to a different processing tile within the same processing die, memory tiles in a different die stack, and memory tiles in a different device. The ratio of memory bandwidth (byte) to floating-point operation (B:F) may improve 50× for accessing the local memory block compared with conventional memory. Additionally, the energy consumed to transfer each bit may be reduced by 10×.
    Type: Grant
    Filed: February 28, 2022
    Date of Patent: May 7, 2024
    Assignee: NVIDIA Corporation
    Inventors: William James Dally, Carl Thomas Gray, Stephen W. Keckler, James Michael O'Connor
  • Patent number: D299302
    Type: Grant
    Filed: August 14, 1986
    Date of Patent: January 10, 1989
    Inventor: Stephen W. Gray