Abstract: Methods, systems, and devices for memory architectures with replacement gate through piers are described. A memory architecture with relatively uniform memory cell thickness may be formed by forming a stack of materials including alternating layers of sacrificial material and dielectric material. The processing steps may include forming piers and forming cavities for pillars through the stack of materials. The pillars and electrodes may be formed within the cavities, and a subset of the piers may be removed. The layers of sacrificial material may be removed. A protective liner may be deposited around the electrodes and the remaining piers before depositing layers of metal in place of the sacrificial material. The cavities exposed by removing the subset of piers may be filled with new piers. The remaining piers are removed, and memory cells may be formed between the pillars and the electrodes. Then the removed piers are replaced.

Abstract: Methods and apparatuses for thin film transistors and related fabrication techniques are described. The thin film transistors may access two or more decks of memory cells disposed in a cross-point architecture. The fabrication techniques may use one or more patterns of vias formed at a top layer of a composite stack, which may facilitate building the thin film transistors within the composite stack while using a reduced number of processing steps. Different configurations of the thin film transistors may be built using the fabrication techniques by utilizing different groups of the vias. Further, circuits and components of a memory device (e.g., decoder circuitry, interconnects between aspects of one or more memory arrays) may be constructed using the thin film transistors as described herein along with related via-based fabrication techniques.

Abstract: Methods, systems, and devices for word line structures for three-dimensional memory arrays are described. A memory device may include word line structures that support accessing memory cells arranged in a three-dimensional level architecture. The word line structures may be arranged above a substrate and be separated from each other by respective dielectric layers. Each word line structure may include word line members and a word line plate that is connected to each word line member. Each word line plate may include a contact that may be coupled with a word line decoder operable to bias the word line plate. To couple the word line plate to the word line decoder, the memory device may include first vias that extend through holes in the word line plates and are coupled with second vias that extend from a respective contact through openings in the word line plates above the contact.

Abstract: Methods, systems, and devices for sparse piers for three-dimensional memory arrays are described. A semiconductor device, such as a memory die, may include pier structures formed in contact with features formed from alternating layers of materials deposited over a substrate, which may provide mechanical support for subsequent processing. For example, a memory die may include alternating layers of a first material and a second material, which may be formed into various cross-sectional patterns. In some examples, the alternating layers may be formed into one or more pairs of interleaved comb structures. Pier structures may be formed in contact with the cross sectional patterns to provide mechanical support between instances of the cross-sectional patterns, or between layers of the cross-sectional patterns (e.g., when one or more layers are removed from the cross-sectional patterns), or both.

Abstract: Methods, systems, and devices for dense piers for three-dimensional memory arrays are described. In some examples, a memory device may include pier structures formed in contact with features formed from alternating layers of materials deposited over a substrate. For example, a memory device may include alternating layers of a first material and a second material. In some examples, the alternating layers may be formed into a pair of interleaved comb structures. Pier structures may be formed in contact with the cross sectional patterns, and may provide mechanical support of cross-sectional pattern of the remaining material. In some examples, the piers may further act as a separator between memory cells or other features of the memory device. For example, the piers may extend into at least a portion of the interleaved comb structures, and may accordingly act as barriers during subsequent depositions of materials.

Abstract: Methods, systems, and devices for buried lines and related fabrication techniques are described. An electronic device (e.g., an integrated circuit) may include multiple buried lines at multiple layers of a stack. For example, a first layer of the stack may include multiple buried lines formed based on a pattern of vias formed at an upper layer of the stack. The pattern of vias may be formed in a wide variety of spatial configurations, and may allow for conductive material to be deposited at a buried target layer. In some cases, buried lines may be formed at multiple layers of the stack concurrently.

Abstract: Methods, systems, and devices for techniques for forming self-aligned memory structures are described. Aspects include etching a layered assembly of materials including a first conductive material and a first sacrificial material to form a first set of channels along a first direction that creates a first set of sections. An insulative material may be deposited within each of the first set of channels and a second sacrificial material may be deposited onto the first set of sections and the insulating material. A second set of channels may be etched into the layered assembly of materials along a second direction that creates a second set of sections, where the second set of channels extend through the first and second sacrificial materials. Insulating material may be deposited in the second set of channels and the sacrificial materials removed leaving a cavity. A memory material may be deposited in the cavity.

Abstract: Methods, systems, and devices for contact formation for a memory device are described. A memory device manufacturing operation may include forming bit lines and word lines in a same step. In some cases, the memory device may include word line contact portions that couple respective word lines with respective word line contacts located below the word lines. For example, the word line contact portions may be located between word lines and a substrate of the memory array. In such cases, the processing step may be used for formation of word lines, bit lines, and word line contact portions. Additionally, or alternatively, the memory device manufacturing operation may include forming a sacrificial ring around bit line contacts, which may isolate bit line contacts from a nitride layer.

Abstract: Methods, systems, and devices for methods to increase cell density using a lateral etch are described. A process to manufacture a memory array may include a lateral wet etch to split a pillar into two stacks of memory cells. In some cases, the manufacturing process may include forming a trench in a vertical stack of layers and forming a memory cell pillar which includes an oxide material, a semiconductor channel material, and an insulating material in the trench. Sidewalls of the pillar may be laterally etched to remove portions of the oxide material and the semiconductor material, which may form two stacks of memory cells, each stack in contact with opposing sidewalls of the trench. In some examples, the manufacturing process may include forming one or more supportive piers within the trench, and the pillar of memory cell material may be formed between pairs of piers.

Abstract: Methods, systems, and devices for trench and multiple pier architecture for three-dimensional memory arrays are described. Manufacturing operations for a memory device may include forming trenches, and subsequently forming multiple types of pier structures extending between the trenches in a first horizontal direction, in a second horizontal direction or both. For example, the trenches may be arranged in a grid-like structure extending in one or more rows and one or more columns. A set of a first type of pier may be formed along each of the trenches, a set of a second type of pier may be formed between adjacent trenches in the first horizontal direction, and a set of a third type of pier may be formed between adjacent trenches in the second horizontal direction.

Abstract: Methods, systems, and devices for buried lines and related fabrication techniques are described. An electronic device (e.g., an integrated circuit) may include multiple buried lines at multiple layers of a stack. For example, a first layer of the stack may include multiple buried lines formed based on a pattern of vias formed at an upper layer of the stack. The pattern of vias may be formed in a wide variety of spatial configurations, and may allow for conductive material to be deposited at a buried target layer. In some cases, buried lines may be formed at multiple layers of the stack concurrently.

Abstract: Methods, systems, and devices for access line grain modulation in a memory device are described. A memory cell stack in a cross-point memory array may be formed. In some examples, the memory cell stack may comprise a storage element. A barrier material may be formed above the memory cell stack. The barrier material may initially have an undulating top surface. In some cases, the top surface of the barrier material may be planarized. After the top surface of the barrier material is planarized, a metal layer for an access line may be formed on the top surface of the barrier material. Planarizing the top surface of the barrier material may impact the grain size of the metal layer. In some cases, planarizing the top surface of the barrier material may decrease the resistivity of access lines formed from the metal layer and thus increase current delivery throughout the memory device.

Abstract: Methods and apparatuses for a cross-point memory array and related fabrication techniques are described. The fabrication techniques described herein may facilitate concurrently building two or more decks of memory cells disposed in a cross-point architecture. Each deck of memory cells may include a plurality of first access lines (e.g., word lines), a plurality of second access lines (e.g., bit lines), and a memory component at each topological intersection of a first access line and a second access line. The fabrication technique may use a pattern of vias formed at a top layer of a composite stack, which may facilitate building a 3D memory array within the composite stack while using a reduced number of processing steps. The fabrication techniques may also be suitable for forming a socket region where the 3D memory array may be coupled with other components of a memory device.

Abstract: Some embodiments include an integrated assembly having a pair of substantially parallel features spaced from one another by an intervening space. A conductive pipe is between the features and substantially parallel to the features. The conductive pipe may be formed within a tube. The tube may be generated by depositing insulative material between the features in a manner which pinches off a top region of the insulative material to leave the tube as a void region under the pinched-off top region.

Abstract: Methods and apparatuses for thin film transistors and related fabrication techniques are described. The thin film transistors may access two or more decks of memory cells disposed in a cross-point architecture. The fabrication techniques may use one or more patterns of vias formed at a top layer of a composite stack, which may facilitate building the thin film transistors within the composite stack while using a reduced number of processing steps. Different configurations of the thin film transistors may be built using the fabrication techniques by utilizing different groups of the vias. Further, circuits and components of a memory device (e.g., decoder circuitry, interconnects between aspects of one or more memory arrays) may be constructed using the thin film transistors as described herein along with related via-based fabrication techniques.

Abstract: Methods and apparatuses for a cross-point memory array and related fabrication techniques are described. The fabrication techniques described herein may facilitate concurrently building two or more decks of memory cells disposed in a cross-point architecture. Each deck of memory cells may include a plurality of first access lines (e.g., word lines), a plurality of second access lines (e.g., bit lines), and a memory component at each topological intersection of a first access line and a second access line. The fabrication technique may use a pattern of vias formed at a top layer of a composite stack, which may facilitate building a 3D memory array within the composite stack while using a reduced number of processing steps. The fabrication techniques may also be suitable for forming a socket region where the 3D memory array may be coupled with other components of a memory device.

Abstract: Methods, systems, and devices for a single plug flow for a memory device are described. In some examples, the memory device may include one or more plugs formed above respective bit line plates. The plugs may include a liner and one or more sacrificial materials that are removed during a subsequent etching operation. Accordingly, pillars may be formed above the plugs, and may be generally aligned with the respective bit line plates.

Abstract: Methods and apparatuses for thin film transistors and related fabrication techniques are described. The thin film transistors may access two or more decks of memory cells disposed in a cross-point architecture. The fabrication techniques may use one or more patterns of vias formed at a top layer of a composite stack, which may facilitate building the thin film transistors within the composite stack while using a reduced number of processing steps. Different configurations of the thin film transistors may be built using the fabrication techniques by utilizing different groups of the vias. Further, circuits and components of a memory device (e.g., decoder circuitry, interconnects between aspects of one or more memory arrays) may be constructed using the thin film transistors as described herein along with related via-based fabrication techniques.

Abstract: Some embodiments include an integrated assembly having a pair of substantially parallel features spaced from one another by an intervening space. A conductive pipe is between the features and substantially parallel to the features. The conductive pipe may be formed within a tube. The tube may be generated by depositing insulative material between the features in a manner which pinches off a top region of the insulative material to leave the tube as a void region under the pinched-off top region.

Abstract: Methods and apparatuses for thin film transistors and related fabrication techniques are described. The thin film transistors may access two or more decks of memory cells disposed in a cross-point architecture. The fabrication techniques may use one or more patterns of vias formed at a top layer of a composite stack, which may facilitate building the thin film transistors within the composite stack while using a reduced number of processing steps. Different configurations of the thin film transistors may be built using the fabrication techniques by utilizing different groups of the vias. Further, circuits and components of a memory device (e.g., decoder circuitry, interconnects between aspects of one or more memory arrays) may be constructed using the thin film transistors as described herein along with related via-based fabrication techniques.