Abstract: A communications device, such as a one-way pager, comprises a receiver having a frequency down-conversion means for frequency converting an input signal using a local oscillator signal generated by a signal generating means, which may comprise a frequency synthesizer. The signal generating means (20) comprises a voltage controlled oscillator (VCO) (50) including an oscillator transistor (68) coupled to dc voltage source (54), frequency determining reactive elements coupled to the oscillator transistor (68) for determining the frequency to be generated, at least one of the reactive elements (80) being adjustable in response to an applied voltage and means (82,84) for phase modulating the oscillator transistor (68) in an opposite sense to that caused by voltage perturbations due to noise in the dc voltage supplied by the dc voltage source (54).

Abstract: A polar loop transmitter in which a negative feedback bias adjusting system is provided to control the bias voltage applied to a differential amplifier which supplies the input envelope information to an amplitude modulator, so that the R.F. modulated output goes to zero for a zero in the input envelope information.The negative feedback bias adjusting system comprises a threshold circuit for deriving a threshold voltage from the D.C. component in the output of the differential amplifier. This enables negative going spikes to be separated from the output waveform and their amplitude used to control the D.C. correction component which is applied to an input of the differential amplifier.

Abstract: A polar loop transmitter having particular, but not exclusive, application in VHF single-sideband radio systems.In order to avoid having to match the amplitude detectors used in known polar loop transmitters, it is proposed as an alternative to provide a subtracting circuit which produces a difference signal from between the low level input signal and the attenuated output signal. The difference signal is amplitude demodulated in a mixer and the demodulated signal is used as a control signal for the amplitude modulator.First and second limiting amplifiers are used to derive the carrier signals from the input and output signals. The outputs of the limiting amplifiers are applied to a phase sensitive detector formed by another mixer whose output is used as a correction signal for a voltage controlled oscillator coupled to the amplitude modulator. The output of the first limiting amplifier is also used as the local oscillator signal for the amplitude demodulator.

Abstract: A polar loop transmitter in which a negative feedback bias adjusting system is provided to control the bias voltage applied to a differential amplifier which supplies the input envelope information to an amplitude modulator, so that the R.F. modulated output goes to zero for a zero in the input.The envelope information negative feedback bias adjusting system modifies a predetermined bias voltage supplied by a potentiometer by sampling and holding the peak value of negative spikes occurring in the output of the differential amplifier and using the held value as a negative feedback voltage to the differential amplifier.

Abstract: An amplifier circuit arrangement comprises an inverting (2) and a non-inverting amplifier (4) connected between a common input (1) and respective inputs of a summing circuit (6). The gains of the amplifiers are unequal for low amplitude input signals but are arranged to produce substantially equal antiphase limited outputs for high amplitude input signals. By making the gains of the amplifiers greater than the difference between their gains, a rapid transition is obtained from a situation where the gain of the arrangement corresponds to the numerical difference between the amplifier gains, to one where it has fallen to a low level. This property can be used in a phase-locked loop of which four examples are given, when the beat frequency output of a phase sensitive detector connected to the input of the amplifier arrangement is large, the output of the summing circuit (6) will be low.

Abstract: The double phase lock loop arrangement of the invention comprises a first feedback loop including a first voltage controlled oscillator (16), a second feedback loop including a second voltage controlled oscillator (20) and first (PSD1), second (PSD2) and third (PSD3) phase sensitive detectors. Each of the detectors have first and second inputs and an output, each first input being coupled to receive a signal which is derived from the first voltage controlled oscillator (16). The second voltage controlled oscillator (20) is connected to the second inputs of the first and second phase sensitive detectors (PSD1, PSD2) and via a phase shifter (21) to the second input of the third phase sensitive detector (PSD3) on whose output a lock signal is produced in response to the signals on its first and second inputs being in a desired phase relationship. The output of the second phase sensitive detector (PSD2) is an A.C.